can you compare an int to a bus in verilog?

Question

I know this is probably trivial, but this is the umpteenth time I've googled it so I'd like to get a definitive answer.

I have the following code in a testbench, so it need not be synthesizable. Will this comparison work as expected?

logic [4:0] bus;

task mytask;
    input int i;
    begin
        if(i == bus)
            $write("Match");
    end
endtask

Did you try it? See http://www.edaplayground.com/x/Vc3 – dwikle Mar 02 '16 at 05:11 — dwikle, Mar 02 '16 at 05:11

score 1 · Accepted Answer · answered Mar 02 '16 at 09:18

As dwikle has pointed out, the answer is yes. But in the spirit of teaching a man to fish, you might like to know why...

In System-Verilog there are 2-state types and 4-state types. 2-states can only take the values 0 and 1; 4-state types can take the values 0, 1, X and Z. logic is a 4-state type; bit is a 2-state type.

You can make "buses" out of either:

logic [7:0] my_4_state_8_bit_bus;
bit   [7:0] my_2_state_8_bit_bus;

These can also be signed or unsigned:

logic signed [7:0] my_4_state_signed_8_bit_bus;
bit unsigned [7:0] my_2_state_unsigned_8_bit_bus;

Type int is merely a predefined, 32-bit, signed, 2-state bus:

int               this_is_the_same;
bit signed [31:0] as_this;

You can assign a 4-state type to a 2-state type. If you assign a 4-state type to a 2-state type, X's and Z's are converted to 0's.

You can compare a 4-state type with a 2-state type. If any bit of the 4-state type is X or Z then the result of the comparison will be 1'bX.

http://www.edaplayground.com/x/Rdu

can you compare an int to a bus in verilog?

1 Answers1