How do I assign one multidimensional array to another in system verilog

Question

In System Verilog, I have:

wire [2:0][1:0] sig1;
wire [2:0][3:0] sig2;

I'm attempting to do:

assign sig1[2:0][1:0] = sig2[2:0][1:0];

NCVerilog tells me:

assign sig1[2:0][3:0] = sig2[2:0][3:0];
                |
ncvlog: *E,MISEXX (acc_llcprdbctl.v,89|48): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].

Is there a way to assign multidimensional arrays?

Edit: Apparently, you can't assign arrays using more than one index. So the above example didn't fully represent what I wanted to do. I wanted to splice the second dimension and assign it to the first.

This could be accomplished if I rearranged the array:

wire [1:0][2:0] sig1;
wire [3:0][2:0] sig2;

assign sig1[1:0] = sig2[1:0];

But for any other more precise splicing, I'd have to use a nested for loop.

Answer 1

You can use a generate block as below.

  generate
    for(genvar i=0; i<3; i++) 
      assign sig1[i][1:0] = sig2[i][1:0];
  endgenerate

Answer 2

From LRM :-

An single element of a packed or unpacked array can be selected using an indexed name.

bit[3:0] [7:0] j; // j is a packed array 
byte k;
k = j[2]; // select a single 8-bit element from j

wire [2:0][1:0] sig1;
wire [2:0][3:0] sig2;

is actually equivalent to

wire [1:0] sig1 [2:0];
wire [3:0] sig2 [2:0];

hence, the tool is unable to do assign sig1[2:0][1:0] = sig2[2:0][1:0];

so You can also define it as

wire [2:0] sig1 [1:0];
wire [2:0] sig2 [3:0];
assign sig1[1:0] = sig2[1:0];