assertion for holding the reset for a long time

Question

I see that assertions are always related to n number of cycles of a clock. Is there any way I can check the duration wrt timescale? Meaning

let's say I want to check if a reset is hold for 100ns or less, how do we write a assert statement for this?

Answer 1

Yes, conceptually you can write an assertion like this, using local variables in SVA.

It may look like this :

property reset_chk;
  time current_time;
  @(rst) (~rst, current_time = $time) |=> ($time - current_time == 100);
endproperty

But this type of assertions, should be avoided, as they are written not wrt clock.

Alternatively, one can always make a reference clock, fast enough to accommodate any such signal timings.

For local variables in assertion, you can read Local Variables in SVA

Answer 2

First I would consider whether SVA was the best way to check this at all.

If you think so, how about creating a dummy clock in the testbench with a suitable period and (via the power of hierarchical naming) use that. A suitable period might be

• 100ns if you were looking for a minimum pulse width

• much faster if you were looking for a maximum pulse width (eg a 10ns period would allow you to check the pulse width was less than 110ns, ie 11 cycles).

Assertions are best done synchronously. That doesn't mean you cannot check asynchronous things, but you still need to sample the signals in question synchronously. So, this way you are sampling your asynchronous signal synchronously, using your dummy clock.

Answer 3

This is asynchronous check. The best way is to check it in traditional way or pure systemverilog instead of using SVA concurrent assertion.

If you want, you can still add immediate assertion for coverage purpose. Quick sample code:

//
task assert_reset_hold_100ns();
  fork : fk1
    begin : blk1
      @(reset);
      $fatal;
    end
    begin : blk2
      #100ns;
      ASSERT_RESET_HOLD_100NS: assert(1);
    end
  join_any
  disable fork;
endtask

// checker
initial forever begin
  wait(reset === 0);
  assert_reset_hold_100ns();
  wait(reset === 1);
  end
//