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Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language () and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - ), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - ) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of , IEEE 1364-2005.

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call questa sim commands from SystemVerilog test bench

I want to call questa sim commands like add wave ,add list, write list from my SystemVerilog test bench task add_files_to_list(); add wave -position insertpoint sim:/top/clk add list sim:/top/clk write list -window…
user3627129
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Converting 0 to Z in register

I'm working with a charlieplexed LED board connected to an FPGA, and I want to convert the register containing 1's and 0's to 0's and z's. For example, 8'b01000000 to 8'bz0zzzzzz. The following code works: LED = 8'b01000000; converted =…
Catherine Holloway
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System-Verilog testbench generate 2 clocks same frequency 90 degrees out of phase

For a system verilog testbench I need to create 2 clocks with the parameters Clock1 = 250MHz, starting phase 0degrees Clock2 = 250MHz, starting phase 90degrees w.r.t. Clock1 I tried the following but it had no effect on the clock generation and both…
Bdog
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How to generate ascending values during randomisation

Please help to resolve one randomization-constraint related issue that I am facing. So in my seqItem, I have a write_addr random variable. This variable controls the location in memory where the data should be written. I want to implement different…
haykp
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Is there a way to exclude some coverpoints from coverage collection in systemverilog?

My coverage contains lot of complex crosses , so I built some coverpoints that I don't really care about them when they stand alone. The coverpoints are appearing on the final report and affecting the coverage percentage. Is there a way to include…
Adi
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using interfaces in systemverilog?

i have written a code in system verilog for interface. but it it giving me the error at clk. the error is Undefined variable clk.... code is error at always(posedge clk) interface simple_bus(input logic clk); // Define the interface …
venkat pasumarti
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Example with super function call in UVM

I have come across this statement and I have used many testbench components with this prototype. super.run_phase(), super.build_phase, super.connect_phase. Can anyone explain with a simple example why we need to call super functions everytime. I…
user1978273
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Creating a Verilog wrapper for System Verilog DUT that contains an interface

Basically, I have a system verilog design that I need to integrate in a simulation framework that's in verilog. So I need to create a wrapper in order to interface with the DUT but am having issues trying to do so. The interface to the DUT has an…
okebz
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UVM phases for transactions objects

I have one question related to UVM phases. As I understood the UVM phases e.g. build_phase, connect_phases, are valid only for uvm_component and is derived classes. That means all classes that derive from uvm_transaction i.e. uvm_sequence,…
haykp
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Call task or function via VPI

I know that it's possible to change the values of signals and variables via the Verilog Programming Interface (VPI). It's also possible to trigger a named event, by doing a vpi_put_value(...) on it. Is it somehow possible to call a function or to…
Tudor Timi
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Systemverilog: $realtime display for different timescale precision

I was trying to print the $realtime for the following timescale setting: `timescale 1ns/10ps initial begin #10; $display(" %0t",$realtime); $display($realtime); end The result that gets prints is: 1000 10 I am just curious as…
ssrinivas
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I am unable to write data in an array of type reg. It is default writing xxxx into this

`include "top.v" `include "c_top.v" module fixture; reg [31:0]F[0:100]; reg [31:0]F2[0:50]; reg [31:0]F3[0:50]; reg [31:0]a,b; reg clk,reset,s; wire [31:0]r_expected,r_actual; wire exception_expected,exception_actual; integer i; integer…
user2856923
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What is the best way to write bit number in Verilog?

For writing the bit in Verilog, which is better in the following writing: Let's say 32 bits data and all 32 bits are set to zero: 1) 32'b0 or 2) 32{1'b0} ? On the other hand, i want to change 5 MSB bit to one: 1) {5'b1,26'b0} or 2)…
Chong Han
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What's the advantage of bit over reg in systemverilog?

Variables in testbench mostly are instantiated as bit rather than reg. But bit is just 2 state variable (0 and 1), reg is 4 state variable (0,1,x and z). Why people used bit as testbench variables? I took over an old project and all the testbench…
TyL
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How can unique-case violations be caught by or report to the test-bench

The goal is to create a mechanism to automatically catch unqiue case violations and have them reported to the test-bench for error counting during simulation. The log files can be huge making post processing less practical. Manually creating…
Greg
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