Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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Ones count system-verilog

I have a wire vector with 64 bits; wire [63:0] sout; I want to compute the sum of these bits or, equivalently, count the number of ones. What is the best way to do this? (it should be synthesizable)

system-verilog

asked Nov 28 '14 at 23:30

Void Star

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How to write a testbench to loop through 4 inputs?

I have to create the Verilog code and testbench for this schematic. I have the design for it here. module prob1(input wire a,b,c,d, output wire out); assign out = (a||d)&&(!d&&b&&c); endmodule Here is what I have for the testbench so…

loops testing verilog system-verilog

asked Oct 05 '14 at 20:42

user2680027

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1 answer

Defining interface inside a package

In IEEE Std 1800-2012 we can find description of packages and such information: Types, nets, variables, tasks, functions, sequences, properties, and checkers may be declared within a package I was wondering, if there is any particular reason why…

system-verilog

asked Aug 08 '14 at 17:20

Qiu

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Are SystemVerilog arrays passed by value or reference?

By default, does SystemVerilog pass arrays by value or reference? For example: int array[5] = '{0,1,2,3,4}; some_function(array); // <-- value or reference?

arrays system-verilog

asked Apr 30 '14 at 18:53

Victor Lyuboslavsky

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134

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2 answers

SystemVerilog foreach syntax for looping through lower dimension of multidimensional array

What is the standard way of looping through the lower dimension of a multidimensional array? With the higher dimension fixed. In the following example: automatic int i = 2; foreach (my_req[i][j]) begin // <-- WARNING $display("i:%0d,j:%0d",…

arrays multidimensional-array foreach system-verilog

asked Apr 17 '14 at 14:48

Victor Lyuboslavsky

9,882
25
87
134

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1 answer

What should '{default:'1} do in system verilog?

I have an array that I would like to initialize to all 1. To do this, I used the following code snippet: logic [15:0] memory [8]; always_ff @(posedge clk or posedge reset) begin if(reset) begin memory <= '{default:'1}; end else…

system-verilog

asked Mar 27 '14 at 19:42

nguthrie

2,615
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2 answers

Handing reset in SystemVerilog assertions

How are the following two properties different? property p1; @(posedge clk) disable iff (Reset) b ##1 c; endproperty property p2; @(posedge clk) (~Reset & b) ##1 c; endproperty assert property (p1); assert property (p2);

system-verilog system-verilog-assertions

asked Feb 20 '14 at 19:11

Ari

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What is parasitic state machine in Johnson counter

module johnson #(parameter N=8) (output logic [N-1:0] q, input logic clk,reset); always_ff @(posedge clk,posedge reset) if(reset) q<=0; else q<={~q[0],q[N-1:1]}; endmodule Above is the systemverilog HDL for an 8-bit…

system-verilog

asked Feb 14 '14 at 23:48

Vaibhav Sundriyal

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2 answers

How to get array of values as plusargs?

How to get the array of values as arguments. I need get an array of commands of undefined size from the command line. How to get these arguments into an array or queue? Eg: +CMDS=READ,WRITE,READ_N_WRITE It should be taken to an array.

command-line-arguments verilog system-verilog

asked Dec 11 '13 at 12:37

bachu

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4 answers

How to define a parameterized multiplexer using SystemVerilog

I am trying to create a module which switches x input data packets to a single output packet according to a one hot input. If x was a fixed value of 4, I would just create a case statement, case (onehot) 4'b0001 : o_data = i_data[0]; 4'b0010 :…

verilog system-verilog

asked Nov 09 '13 at 12:23

user2646276

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2 answers

How do I access an internal reg inside a module?

I have this architechture/topology in Verilog: How can I access the internal reg IntReg, that isn't a input/output in IntModule, in SystemVerilog? always @(posedge clk) begin $display ("[Time %0t ps] IntReg value = %x", $time,…

verilog system-verilog

asked Aug 27 '13 at 19:20

Filipe Utzig

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2 answers

returning queue from function in systemverilog

I can't compile this code: function integer[$] get_register_name; integer ret[$]; ret.push_back(1); ret.push_back(2); return ret; endfunction Is it possible to return a…

system-verilog

asked Dec 20 '12 at 01:28

e19293001

2,783
9
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54

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2 answers

Why are nonblocking assignments not allowed in Verilog functions?

I have read that use of nonblocking assignments is not allowed in Verilog functions. Can anyone suggest a plausible explanation for this?

verilog system-verilog hdl

asked Aug 20 '12 at 10:23

Akash

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2 answers

Are there any good dependency management tools that aren't language specific?

I'm looking for dependency management tool that isn't specific to Java or any other language. We use SystemVerilog, a hardware description language, to create stand-alone modules. We tag releases of those modules at various milestones. Higher level…

dependency-management system-verilog

asked Mar 02 '12 at 22:50

Chris

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3 answers

systemverilog unpacked array concatenation

I'm trying to create an unpacked array like this: logic [3:0] AAA[0:9]; I'd like to initialize this array to the following values: AAA = '{1, 1, 1, 1, 2, 2, 2, 3, 3, 4}; For efficiency I'd like to use repetition constructs, but that's when things…

system-verilog

asked Mar 24 '20 at 19:31

dsula

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