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I have read that use of nonblocking assignments is not allowed in Verilog functions. Can anyone suggest a plausible explanation for this?

toolic
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Akash
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2 Answers2

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The IEEE Std for Verilog (1364-2001), section "10.3.4 Function rules" states:

A function shall not have any nonblocking assignments.

The 1800-2009 IEEE Std elaborates more on this:

Functions shall execute with no delay. Thus, a process calling a function shall return immediately. Statements that do not block shall be allowed inside a function; specifically, nonblocking assignments, event triggers, clocking drives, and fork-join_none constructs shall be allowed inside a function.

The intention was for functions to be simple to evaluate in the Verilog event queue. If you need to advance time, use a task instead of a function.

toolic
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Try not to think about functions in Verilog like functions in C:

Functions in Verilog are designed to be a developer-friendly way to instantiate identical combinational logic in multiple places at once rather than having to write it over again / make a module for it. A lot of "newbies" to Verilog try to rationalize functions like they are C functions, and while they are "returning" a value, it is easier (and more correct) in the end to conceptualize them as blocks of combinational gates.

Note that this is different from a "task", which are more generally used for executing things "in order", which would probably be more useful in a testbench situation than a function

As you learn Verilog try not to rationalize the HDL you write as "code", because it is a different style of thinking.

EDIT: Took out some bad explanation on my part

omicron
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    In testbenches it still doesn't make sense to have blocking assignments in functions. Functions are NOT software functions, even in testbenches. While even in something like SystemVerilog testbenches can be very "software"-like, they still are representing hardware, if very abstractly. – omicron Aug 21 '12 at 15:27
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    You have the terminology wrong between blocking and nonblocking. And your rationale is doubtful. Functions are unte – Jan Decaluwe Aug 24 '12 at 06:28
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    ... Functions are intended to work as in software in the first place. – Jan Decaluwe Aug 24 '12 at 06:42
  • Tasks and functions are different. Tasks are designed to execute "in order" like software. Functions act like combinational logic. Unless you are writing Verilog that only lives in simulator land this difference actually matters. (Fixed the confusion above) – omicron Aug 24 '12 at 15:37
  • @omicron Functions don't have side effects, tasks (procedures) do. Purely a software notion. – Jan Decaluwe Aug 25 '12 at 09:50
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    The question wasn't specific to synthesis and verilog functions are clearly designed to mimic those from languages like C. –  Aug 29 '12 at 16:52