Stack Overflow
Stack Overflow

Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language () and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - ), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - ) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of , IEEE 1364-2005.

3298 questions
6
votes
3 answers

What is the point of a "plain" begin-end block?

I'm reading some third party Verilog, and found this: function [31:0] factorial; input [3:0] operand; reg [3:0] index; begin factorial = operand ? 1 : 0; for(index = 2; index <= operand; index = index + 1) …
Randomblue
  • 112,777
  • 145
  • 353
  • 547
6
votes
6 answers

Assign ASCII character to wire in Verilog

I understand that you can declare a string in a Verilog test bench as follows: reg [8*14:1] string_value; initial string_value = "Hello, World!"; I can then do things with this string, like use $display in a test bench to display it. I…
Kevin Vermeer
  • 2,736
  • 2
  • 27
  • 38
6
votes
2 answers

Exporting tasks to 'C using DPI

I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things Register Read Register Write Interrupt handler As I understand, register reads and writes are…
Alphaneo
  • 12,079
  • 22
  • 71
  • 89
6
votes
3 answers

Difference between 1 and 1'b1 in Verilog

What is the difference between just giving 1 and giving 1'b1 in verilog code?
Yashwanth Gopinath
  • 87
  • 1
  • 1
  • 2
6
votes
1 answer

Is recursive instantiation possible in Verilog?

Some problems lead themselves to a recursive solution. Is recursive instantiation possible in Verilog? Is it possible for a module to instantiate itself?
Matthew Taylor
  • 13,365
  • 3
  • 17
  • 44
6
votes
3 answers

Do any open source, complete system verilog grammars exist?

Are there any grammars for system Verilog that are open source? I'm looking for System Verilog, not plain Verilog grammars.
Ross Rogers
  • 23,523
  • 27
  • 108
  • 164
6
votes
2 answers

In systemverilog # delay fails when RHS signal changes faster than delay

Following code in systemverilog fails: module test_dly; reg clk = 0; wire w_clk_d; always #1ns clk <= ~clk; assign #1400ps w_clk_d = clk; endmodule I expected that w_clk_d will be delayed version of clk, but it is not. Seems that # not…
Albert Waissman
  • 71
  • 1
  • 1
  • 5
6
votes
5 answers

What is the difference between using an initial block vs initializing a reg variable in systemverilog?

What is the difference between the following two examples with regards to simulation? A) reg a; initial a = 1'b0; and B) reg a = 1'b0; Is it different for logic variables?
supernun
  • 437
  • 1
  • 6
  • 16
6
votes
2 answers

What's the general procedure for compiling an HDL Program for an FPGA?

I have a question regarding the compilation of HDL programs within the context of FPGA design. 1) Why does the compilation process take so long? Is it really the compilation process that takes a long time, or is it the writing of individual logic…
Izzo
  • 4,461
  • 13
  • 45
  • 82
6
votes
2 answers

Can I call a VHDL function inside Verilog

I am currently trying to use certain legacy VHDL codes into my Verilog design. While it is possible to instantiate VHDL modules within Verilog, I could not find a way to call VHDL functions within Verilog. (Apart from wrapping it around in a VHDL…
Pulimon
  • 1,776
  • 4
  • 31
  • 45
6
votes
1 answer

Is there any recommended way to automate module port connection?

I'm trying to understand or research about the best practices of ASIC design in verilog. I'm working on a medium size block with ~20 sub modules (each ~1000 lines of code). It's a painstaking job to manually instantiate all the sub-module and do…
newbie
  • 4,639
  • 10
  • 32
  • 45
6
votes
1 answer

Usage of Clocking Blocks in Systemverilog

What is the exact usage of Clocking Blocks in System Verilog, and how does it differ from normal always @ (posedge clk) block? Some differences, which I know : Clocking Block samples input data from Preponed Region, whereas in normal always…
Karan Shah
  • 1,912
  • 1
  • 29
  • 42
6
votes
2 answers

What are the uses of force - release statements?

From a hardware point of view, what do force and release statements model? What are the uses of these statements?
pradeep
  • 3,005
  • 12
  • 42
  • 65
6
votes
2 answers

Doxygen alternative for Verilog, SystemVerilog?

Project "doxverilog" is not supported more, author's site is not responding. Project http://intelligentdv.com/downloads/index.html#doxygentools works only for SV class hierarchy. AMIQ http://www.dvteclipse.com/ Specador is enterprise overpriced…
Mike I.
  • 91
  • 1
  • 2
  • 5
6
votes
6 answers

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry…
Brian Carlton
  • 7,545
  • 5
  • 38
  • 47
1 2 3
…
99 100