module johnson #(parameter N=8)
(output logic [N-1:0] q, input logic clk,reset);
always_ff @(posedge clk,posedge reset)
if(reset)
q<=0;
else
q<={~q[0],q[N-1:1]};
endmodule
Above is the systemverilog HDL for an 8-bit Johnson counter. I read from a textbook that it has large number of unused states that form a counter of their own i.e a parasitic state machine. What exactly is this parasitic state machine?