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In IEEE Std 1800-2012 we can find description of packages and such information:

Types, nets, variables, tasks, functions, sequences, properties, and checkers may be declared within a package

I was wondering, if there is any particular reason why interfaces can't be defined inside a package? It seems to me that it might be useful, but apparently the creators of the standard wouldn't agree.

AndresM
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Qiu
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1 Answers1

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The main reason has to do with the different namespaces that exist in SystemVerilog, and requirements for separate compilation. Interfaces are one kind of design element (See the 1800-2012 LRM section 3.2 Design elements) whose definitions exist in their own namespace and do not require compilation before use. Packages were intended for types that have a specific compilation order requirement as well as create a separate namespace. Over the different revisions of the standard, that original intent may have been lost.

Verilog has a configuration mechanism that allows you to have different implementations of the same design elements existing in different libraries.

Chiggs
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dave_59
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  • +1 for context and "original intent may have been lost"! So many asymmetries in SystemVerilog rules for interfaces, packages, modules it's difficult for those not involved in the standards committee to understand or infer the reasoning... Why can't I parameterise a package? Why can't a I pass a module or interface as a parameter? To a typical user these seem like oversights but perhaps these were concious decisions! – Chiggs Aug 13 '14 at 08:51
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    SystemVerilog is a great example of feature creep. Each feature on their own seems like a good idea, but in the big picture of things, makes things worse with unnecessary complexity. This happens not only in the committee, but vendors that either implement extensions, or bugs that become extensions that have to get incorporated back into the standard. – dave_59 Aug 13 '14 at 15:44
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    Agreed. With SV we seem to have ended up with something that still doesn't allow nice abstractions for synthesisable RTL but also isn't a very good software language, making verification messy too. – Chiggs Aug 14 '14 at 14:48