Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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2 answers

Implicit net-type declaration and `default-nettype

I have a question on `default_nettype directive of SystemVerilog. By default, the following code is ok. module m1 ( input logic i1, output logic o1 ); logic l1; assign l1 = i1; assign o1 = l1; endmodule However, when I change…

system-verilog

asked Oct 22 '19 at 07:54

Hiroto Kagotani

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2 answers

In SystemVerilog, what does (.*) mean?

I have a testbench declared as module test_circuit logic a,b,c; logic y; circuit UUT (.*); //what does this line mean? initial begin //something here end endmodule I haven't found any tutorials which tell me what it…

system-verilog

asked Oct 17 '19 at 15:38

Papbad

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1 answer

when are assertion "disable iff" values evaluated?

For this code, I see both assertions fail. It seems that disable iff (value) is evaluated later than the expression itself. Can someone explain this. module tb(); reg clk = 1; always #5 clk = !clk; reg rst = 1; always @ (posedge clk) rst <=…

system-verilog system-verilog-assertions

asked Apr 18 '18 at 01:40

nachum

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3 answers

Why does system verilog max() and min() functions return a queue and not a single element?

I noticed this interesting thing about the max() and min() functions in SV LRM (1800-2012) 7.12 (Array manipulation methods). I tried out the max() and min() functions in a dummy SV file int a[3] = {0,5,5}; int q[$]; int b; q = a.max(); // legal b =…

system-verilog

asked Nov 16 '17 at 20:48

Prashanth R

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1 answer

How is SystemVerilog 0 different from '0?

When executing the following piece of SystemVerilog code (compiled and run with Questa) bit [7:0] test = 255; $display("%b %b %b", test, test == 255, test == '1); $display("%b %b %b", ~test, ~test == 0, ~test ==…

system-verilog

asked Apr 12 '17 at 14:29

PieterNuyts

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1 answer

systemVerilog - round real type

What is the best way to round a real type in systemVerilog according: Case positive: if fraction >= 0.5 ---> round return the "integer part" + 1 (for example 4.5 --->5) if fraction < 0.5 ---> round return the "integer part" (for example 4.2…

rounding system-verilog

asked Feb 02 '17 at 13:53

sara8d

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2 answers

uvm_event and system verilog event difference

What is the advantage of uvm_event over the SystemVerilog event ? Can someone explain with small pseudo code ?

system-verilog uvm

asked Sep 07 '16 at 02:56

Ashutosh Rawal

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1 answer

Verilog signed multiplication: Multiplying numbers of different sizes?

For some reason I have been unable to find any definitive resources or stackoverflow questions answering this: Does verilog take care of input and output dimensions when multiplying signed numbers? To be specific, what happens if I multiply a…

verilog system-verilog

asked Jun 19 '16 at 15:47

sirblobfish

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1 answer

How does SystemVerilog `force` work?

I have a hierarchy of modules where I am trying to do a force to get different value at different module interface. I am working on a component whose task is to inject transaction to a module down the hierarchy, bypassing the drives from the modules…

verilog system-verilog

asked Jun 12 '16 at 12:57

Gautam

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2 answers

Python: print base class variables

I'm using a library to share data between C++, VHDL, and SystemVerilog. It uses codegenerators to build datastructures that contain the appropriate field. Think of a c type data structure. I want to generate python code that contains the…

python inheritance vhdl code-generation system-verilog

asked Nov 11 '15 at 10:43

Maurice

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3 answers

What does " ref " mean in systemverilog?

I found this in systemverilog: task automatic xxx(ref xxxpackage bus,input interface ift); I want to know the usage of ref. What is the advantage?

system-verilog

asked Jun 24 '15 at 04:28

bunch

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1 answer

How to use throughout operator in systemverilog assertions

Here is a spec: If signal a is asserted then it must be asserted till signal b is asserted and then it should de-assert on next clock edge. I'm reading through 16.9.9 of LRM (as well as http://www.testbench.in/AS_06_SEQUENCES.html) and the way I…

system-verilog assertions system-verilog-assertions

asked Jun 08 '15 at 00:35

wisemonkey

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2 answers

Format specifications for real numbers

I would like to print some real numbers to a log file. To make them easy to read I would like them to all have the same width. I know these numbers will range from 0 to 4095.75 so I tried this: $display("expected= %4.2f, actual= %4.2f", expected,…

verilog system-verilog

asked Apr 28 '15 at 17:23

nguthrie

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Do all Flip Flops in a design need to be resettable (ASIC)?

I'm trying to understand clock-reset in a chip. In a design what criteria are used to decide whether a flop should be assigned to a value (typically to zero) during reset? always_ff @(posedge clk or negedge reset) begin : process_w_reset …

vhdl verilog system-verilog asic

asked Apr 11 '15 at 04:02

newbie

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Passing a module name as parameter

I want to create this generic wrapper for a bunch of modules I am writing. The wrapper should provide the ability to connect these modules to different type of NoCs without having to change the behavior of the inner modules. I thought that one way…

hardware verilog system-verilog register-transfer-level

asked Apr 10 '15 at 20:57

igon

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