Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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Error (10028): Can't resolve multiple constant drivers and Error (10029): Constant driver

I am new to Verilog, and trying to write a traffic light code where the LED light changes after certain time. I'm keep getting on different errors while compiling. I tried to fix them by changing the arrangement, or variables in the code, but it…

error-handling verilog quartus intel-fpga

asked Nov 03 '22 at 06:15

Doyeon.K

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1 answer

Compilation of verilog code in quartus prime takes much longer after adding block

I am attempting to make the snake game in verilog using my DEE-10 Lite and compiling using Quartus Prime (Lite Edition Version 20.1.1). The Analysis and Synthesis time takes almost 10 times longer after adding the following for loop: for (i = 0); i…

verilog fpga quartus intel-fpga

asked Dec 13 '21 at 01:56

Jessey H

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1 answer

The clock speed is two times faster when the clock duty cycle is 50%

I want to generate 102Hz clock on a FPGA board(the one with cyclone 3） the original clock on the hardware is 50MHz, so I divided it by 490196 to get 102Hz clock but the clock speed is two times faster when I set the duty cycle to 50% signal…

vhdl verilog fpga quartus intel-fpga

asked Dec 09 '21 at 12:25

Gordon Z

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1 answer

Which files or folders should be in .gitignore in Quartus Prime 18.1 Lite (Verilog) project?

I wish to know which files, extensions and/or folders are cache data that are generated again every time that I compile the project!

git gitignore quartus

asked Sep 25 '21 at 21:46

Lincoln

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1 answer

DE-10 FFMPEG Raw YCbCr 4:2:2 Frame to PNG or Video leads to bad result

So i am trying to record analog video from analog-video in port of the DE10-standard board. the raw frames are 4:2:2 720x480 hence frame size should be 720*480 * 2 = 691200bytes,however i get 2 more bytes with hex value 0 at the beginning of the…

video ffmpeg quartus intel-fpga

asked May 21 '21 at 21:51

Anouar Touati

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1 answer

How to generate a synthesizable pseudo random generator from 1 to 52 System Verilog

Could someone explain how to create a pseudo number generator that has a range of 1 to 51 and can have its value placed within something like the for loop. This has to be in System Verilog and synthesizable. I have read about some CRC and LFSRs but…

system-verilog quartus

asked May 02 '21 at 23:26

TonyDaStudent

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2 answers

Left bit shifter in VHDL

I need to create a left bit shifter in VHDL using if then statements. I am not sure what to do from what ive already written. I've attached photos and the code below. Thanks a ton! My Code The problem im trying to do LIBRARY ieee; USE…

vhdl quartus

asked Feb 18 '21 at 18:32

Max Sorin

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1 answer

Adding an input carry then generating a sum and a carry

For 4'b1011 I need to add an input carry and generate a sum and a carry. I keep getting an error message saying that a value cannot be assigned to input carry_in whenever I try to compile the code, so I am not sure on what I am doing wrong with the…

verilog quartus

asked Feb 02 '21 at 02:40

Alan Terrazas

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3 answers

Cause of inferred latches (not else or default statement) in Verilog

Quartus is telling me that I have inferred latches for input_val, ii, output_val, delayed, and addr_to_rom. I have looked at previous posts and made changes so that all my if statements have an else component and that my case statement has a default…

verilog system-verilog quartus

asked Aug 04 '20 at 19:28

Tarashi99

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3 answers

Error while reading a file from memory in Quartus prime

I am trying to read a .txt file, stored in my computer in Quartus Prime using the "$readmemh" function, but it doesn't seem to work. I am getting an error like. Error (10054): Verilog HDL File I/O error at scratch.v(8): can't open Verilog Design…

verilog fpga quartus

asked Jun 15 '20 at 08:51

Dip Chakraborty

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1 answer

I'm getting the following error when compiling in Quartus: Error (10663):

I'm programming an FPGA (New to verilog and Quartus) However, I get the following errors: Error (10663): Verilog HDL Port Connection error at ALU_pv.v(7): output or inout port "alu_out" must be connected to a structural net expression Error…

verilog fpga quartus

asked Feb 24 '20 at 06:04

Adam Griffin

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1 answer

Verilog HDL syntax error near "default", expecting "endmodule"

// ProgramCounterTestBench timescale 1ns / 1ps module ProgramCounterTestBench(); logic Clock = 0; logic Reset = 0; logic [15:0] LoadValue; logic LoadEnable; logic signed [8:0] Offset; logic …

testing verilog fpga modelsim quartus

asked Dec 11 '19 at 23:14

Bernardo Silva

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1 answer

How can i use generic array type with modelsim?

It's my first question here, I really hope you can help me Edit 03 December 2019 : We resolved our problem with the declaration type, but now, we have other problem So, when I tried to run my testbench for the simulation on modelsim, we got these…

vhdl modelsim quartus

asked Nov 18 '19 at 19:47

Elmatador25

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1 answer

How to fix Error (10170): Verilog HDL syntax error at near text "("; expecting ";"

I am trying to instantiate a NiosII core in Quartus II and get the following compilation error message: Error (10170): Verilog HDL syntax error at myNiosII_inst.v(1) near text "("; expecting ";" I added myNiosII.qip and myNiosII_inst.v files to my…

verilog system-verilog intel-fpga quartus nios

asked Nov 12 '19 at 15:01

b7031719

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1 answer

VHDL What does this error mean, Net, "Name", which fans out to "name", cannot be assigned more than one value

Part of my project is to design a 16bit Multiplier with an arrayMultiplier structure. In this array Multiplier instead of using 1 bit adders, I made a 16bit Adder (which is working, I've done simulations). I'm using it as a component in the…

vhdl quartus

asked Apr 24 '19 at 23:31

TheCoolest2

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