I'm getting the following error when compiling in Quartus: Error (10663):

Question

I'm programming an FPGA (New to verilog and Quartus) However, I get the following errors:

Error (10663): Verilog HDL Port Connection error at ALU_pv.v(7): output or inout port "alu_out" must be connected to a structural net expression
Error (10663): Verilog HDL Port Connection error at ALU_pv.v(7): output or inout port "Cout" must be connected to a structural net expression

This is my top level entity:

module ALU_pv (input [3:0] aluin_a, OPCODE, input Cin, output reg [3:0] alu_out, output reg Cout, output OF);


wire[3:0] aluin_b; assign aluin_b = 4'b0011;

ALU alu1(aluin_a, aluin_b, OPCODE, Cin, alu_out, Cout, OF); //error is calling out here

endmodule

I'm instantiating to this ALU:

// //ALU

module ALU (input [3:0] aluin_a, aluin_b, OPCODE, input Cin, output reg[3:0] alu_out, output reg Cout, output OF);

reg[3:0] Bin;
wire [3:0] Bn, S;
wire Co;

com2s C1(aluin_b, Bn);
FA4 FA1(aluin_a, Bin, Cin, S, Co, OF);

always @ (*) begin
  Bin= 4'b0000; alu_out= 4'b0000; Cout= 'b0;
  case (OPCODE)
    4'b1000 : begin                     //A+B
        Bin = aluin_b; alu_out = S; Cout = Co;
       end
                        // A+B+Cin : add with Cin
    4'b1001 : begin
    Bin = aluin_b; alu_out = S; Cout = Co;
    end


    4'b1010 : begin                 // Subtract b-a
    Bin = aluin_b; alu_out = S; Cout = Co;
    end

////Bitewise Functions////////////////////////////////////
                        // NAND
    4'b0000 : begin
    alu_out= ~(aluin_a & aluin_b);
    end


                        // NOR
    4'b0001 : begin
    alu_out= ~(aluin_a | aluin_b);
    end

                        // XOR
    4'b0010 : begin
    alu_out= aluin_a^aluin_b;
    end

                        // NOT
    4'b0100 : begin
    alu_out= ~aluin_a;
    end

                        // Rightshift
    4'b0101 : begin
    alu_out= aluin_a >> 1;
    end

    default : begin
    alu_out = 0; Cout = 0;
      end

  endcase
end
endmodule







//Ripple Adder
module FA4( input [3:0] aluin_a, aluin_b, input Cin, output [3:0] Sum, output Cout, OF);
wire Cout1, Cout2, Cout3;

 FA fa1 (aluin_a[0], aluin_b[0], Cin,   Sum[0], Cout1);
 FA fa2 (aluin_a[1], aluin_b[1], Cout1, Sum[1], Cout2);
 FA fa3 (aluin_a[2], aluin_b[2], Cout2, Sum[2], Cout3);
 FA fa4 (aluin_a[3], aluin_b[3], Cout3, Sum[3], Cout);
 xor X1 (OF, Cout3, Cout);
endmodule


//2's Comp
module com2s ( input[3:0] aluin_b, output [3:0] Bn);
 wire [3:0] Bn1;
 wire OF, Cout;
 assign Bn1=~aluin_b;
 FA4 fa1 (Bn1, 4'b0000,1'b1, Bn, Cout, OF);
endmodule


//Full Adder
module FA (input aluin_a,aluin_b,OPCODE, output Sum, Cout);
 wire Sum1, Cout1, Cout2;
 HA ha1 (aluin_a,aluin_b, Sum1, Cout1);
 HA ha2 (Sum1, OPCODE, Sum, Cout2);
 or O1(Cout, Cout1, Cout2);
endmodule



//Half Adder

module HA (input aluin_a,aluin_b, output Sum, Cout);
 assign Sum= aluin_a^aluin_b;
 assign Cout= aluin_a&aluin_b;
endmodule

I Assume its a port error but i'm not sure where?

`FA4 fa1 (Bn1, 4'b0000,1'b1, Bn, Cout, OF);` has six arguments but FA has only five. — Oldfart, Feb 24 '20 at 17:01

score 2 · Answer 1 · answered Feb 24 '20 at 07:33

2

In Verilog, module output ports can only be connected to wire not reg. Your ALU output ports drive and are connected to ALU_pv output ports, which are also declared as reg. You need to change ALU_pv to output wire [3:0] alu_out.

Also see http://go.mentor.com/wire-vs-reg

answered Feb 24 '20 at 07:33

dave_59

39,096
3
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If I change output wire [3:0] alu_out , this will cause an implicit net alu_b . Also, ALU_pv , is assigning 4'b0011 to the FPGA. However, I did give it a try and still the same error. – Adam Griffin Feb 24 '20 at 13:40
There is no `alu_b` in the example. Fixing this one error will probably expose other but different errors. – dave_59 Feb 24 '20 at 17:28

I'm getting the following error when compiling in Quartus: Error (10663):

1 Answers1