For 4'b1011 I need to add an input carry and generate a sum and a carry. I keep getting an error message saying that a value cannot be assigned to input carry_in whenever I try to compile the code, so I am not sure on what I am doing wrong with the code below.
4'b1011: begin out = inp1 + inp2; //adds an input carry, generates a sum
& carry
if (inp1 +inp2 > 1111)
carry_in = 1; //figure out why carry_in =1 is blocking code from running
else
carry_out <= carry_in;
end
Below is the rest of the ALU that goes along with the code above
module lab1(inp1, inp2, sel, out, carry_in, carry_out);
input[3:0] inp1, inp2, sel, carry_in;
output[3:0] out, carry_out;
reg[3:0] out, carry_out;
always @(inp1, inp2, sel, carry_in)
begin
case(sel)
4'b0000: begin out = inp1 + inp2; end // Addition
4'b0001: begin out = inp1 - inp2; end // Subtraction
4'b0010: begin out = inp1 - 1; end // Subtract by 1
4'b0011: begin out = inp1 + 1; end // Add by 1
4'b0100: begin out = inp1 & inp2; end // Logical AND
4'b0101: begin out = inp1 | inp2; end // Logical OR
4'b0110: begin out = ~ inp1; end // LOGICAL NOT
4'b0111: begin out = (inp1 ^ inp2); end // XOR
4'b1000: begin out = inp1 << 4'b0010; end // Logical shift Left
4'b1001: begin out = inp2 >> 4'b0011; end // Logical shift Right
4'b1010: begin out = inp1 + inp2; //generating a sum & carry
if(inp1 + inp2 > 1111) //if the sum is greater than 1111
carry_out = 1; //carry_out is 1
else //carry_out = 0
carry_out <= carry_in;
end
4'b1011: begin out = inp1 + inp2; //adds an input carry, generates a sum
& carry
if (inp1 +inp2 > 1111)
carry_in = 1; //figure out why carry_in =1 is blocking code from running
else
carry_out <= carry_in;
end
4'b1100: begin //subtraction using two's complement
if(inp2 > inp1)
out <= ~inp1 + 1 - inp2;
else
out <= inp1 - inp2; //subtraction
end
4'b1101: begin //Comparing two 4-bit inputs
if(inp1 == inp2) //checks if inp1 is equal to inp2
out = inp1 || inp2;
else
if(inp1 > inp2) //checks if inp1 is greater than inp2
out = inp1;
else
out = inp2; //if inp1 is not >= to inp2 then it inp2 is greater
end
default: begin out = 4'b0000; end // This line is very important
endcase
end
endmodule