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Part of my project is to design a 16bit Multiplier with an arrayMultiplier structure. In this array Multiplier instead of using 1 bit adders, I made a 16bit Adder (which is working, I've done simulations). I'm using it as a component in the multiplier.

Note I have attach my last name to every variable according to the professor, please ignore that

I have to put it into a pastebin cause it's too long for posting. Please ignore the comments that say like +16, FA, -1. This is for me to just follow a diagram for proper indexing.

This is an example diagram https://d2vlcm61l7u1fs.cloudfront.net/media%2F27b%2F27b41d2f-aa6c-4a81-bdc0-16ff1c681fc7%2FphpQ0V3VI.png

**REDACTED ** Third is the error itself

Code Redacted

https://pastebin.com/tZ6ptLYp

I'm not sure what the error is saying so I can't solve the issue. Been working on this for hours so maybe I'm just tired and am not seeing it. Thanks

TheCoolest2
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    You don't provide a [mcve] in the question itself, and the linked truncated source file 16bitmultiplier.txt that will be deleted in 6 days is not valid VHDL (even removing the back ticks and commenting out the ...). There are VHDL semantic issues that you could address with a simulator's analyzer (compiler) hopefully providing useful error messages. (For instance port map aspect actuals *shall* be locally static names (IEEE Std 1076-2008 6.5.7.3 Port map aspects), they are globally static using indexes supplied by a for generate parameter (9.4.3 Globally static primaries, para 1 d) and s)). –  Apr 25 '19 at 08:34

1 Answers1

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The problem is that you bind multiple wires to the same output wire.

For example :

Line 57 : ... Arena_16bitOUT_Cout_fa => Arena_Cout_vec(0) ...
Line 61 : ... Arena_16bitOUT_Cout_fa => Arena_Cout_vec(0));

I guess it is just copy/paste errors. I did not read all the logic but if it is not the case, you will need some multiplexing logic.

Ayoub Bargach
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