Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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1 answer

Programming Altera DE2 for displaying colors on LCM in VHDL

Hi, i'm coding the main program structure for my LCM, called DE2_LCM2(in vhdl). Within the main structure, there is a clock divider calls PLL2 (in verilog) and a I2S_LCM_Config (in verilog). My PLL2.v and I2S_LCM.v are given by vendor, except for…

vhdl quartus

asked Jul 30 '14 at 03:23

user317130

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2 answers

Using Non-zero indexed Memory in Quartus (Verilog)

I am writing a memory system for a basic 16-bit educational CPU and am running into issues with Quartus Synthesis of my module. Specifically, I have broken down the address space into a few different parts and one of them (which is a ROM) is not…

memory verilog system-verilog synthesis quartus

asked Jul 29 '14 at 06:47

Unn

4,775
18
30

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1 answer

Error on real time simulation Quartus II

I'm learning how to use the time simulation on Quartus II to see the real delays in a circuit, and an error has occurred. This error says that I'm not respecting the hold time for the flip-flop. In the logic simulation the circuit works. Down you…

time simulation verilog digital-logic quartus

asked Mar 20 '14 at 18:07

Guilherme Stéfano

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2 answers

Running timing simulation in modelsim

I've created a small design in Verilog and now i want to run timing simulation. Since I know how to do it for VHDL files, I figured I'll do it (almost) the same way. Unfortunately, it's not that easy. I've compiled my design and received .sdo and…

simulation verilog modelsim quartus

asked Jul 22 '13 at 13:49

Qiu

5,651
10
49
56

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2 answers

Can't infer register because its behavior doesn't match any supported model in Quartus II

The code: library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity decoder10 is port( in_data: in STD_LOGIC_VECTOR (7 downto 0); …

vhdl quartus

asked Apr 30 '12 at 20:58

brommer

-1

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1 answer

Can't infer register in Quartus II (VHDL)

This is the full code library ieee; use ieee.std_logic_1164.all; entity move_key_detector is PORT( clk : IN STD_LOGIC; done : IN STD_LOGIC; hex : IN STD_LOGIC_VECTOR(7 DOWNTO 0); up, down : out std_logic …

vhdl intel-fpga quartus

asked Nov 18 '11 at 20:38

CppLearner

16,273
32
108
163

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0 answers

Accessing RAM (Quartus IP generated) in VHDL

Greets, Environment: Quartus Prime Lite v22.1 Target device: Cyclone 10 LP (10CL025YU256) I am struggling with a project using VHDL to program a Cyclone 10 LP that resides in a Siemens technology card on a PLC rack. To clarify, I am not an embedded…

vhdl ram quartus

asked Aug 24 '23 at 17:54

Graeme Lee

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Quartus SDRAM Controller Core output lagging and/or rdvalid signal wrong

I'm writing a simple RAM and VGA testing module. At first data gets written to the SDRAM (repeatedly 0 to 4095) and then it's read from the sdram and written to a FIFO to show it as pixels on the 4 bit VGA. Because it didn't work properly I analyzed…

vhdl quartus

asked Aug 14 '23 at 20:14

TimSch

1,189
1
12
27

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Quartus Prime (SystemVerilog) - Why does a testbench have to be synthesizable to simulate using ModelSim?

I am trying to verify the functionality of a 32-bit adder module using a testbench. I want to test the adder using random inputs and the testbench code is as follows: `timescale 1ns/1ps module adder_tb(); parameter N = 32; logic [N-1:0] a,…

verilog system-verilog fpga modelsim quartus

asked Aug 05 '23 at 07:59

anuki16

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1 answer

Using an entity from a different project (vhdl) (error: 10481)

I need to use an entity 'task3' from a different project 'lab3' the file name I need it from is also 'task3'. My current project is 'lab4'. The following is the current code for lab4. library ieee; use ieee.std_logic_1164.all; use…

vhdl hdl quartus

asked Mar 09 '23 at 20:38

Boo Man

-1

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1 answer

Verilog - output exuals to XXXXXXXX

I'm trying to design a 32-bit ALU. While simulating using Modelsim output R becomes mixed with x's and 0's like this, at time=20 the addition is calculated and at time=40, substraction is calcualted. In the ALU I'm only calling 3 modules. Adder,…

verilog fpga quartus intel-fpga

asked Dec 09 '22 at 19:03

questionhead

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1 answer

Error (12006): Node instance "" instantiates undefined entity ""

I want to compile a CPU written in Verilog, but for some reason I can't. The source code is this Github. Only system.v received an error that clk_out was covered with capital letters, so I changed it to clk_out_lower. I changed it to clk_out_lower. …

verilog quartus

asked Dec 06 '22 at 07:02

Satoshi921

-1

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1 answer

why does my Verilog adder-subtractor fail the addition here with 1 more than correct answer?

I wrote a 4-bit full-adder-subtractor, and my code managed to operate subtraction but failed operating addition with 1 more than the correct answer: 0101+0101=1011. Help! Here's the full-adder-subtractor code: module Add_sub(x,y,co,u,en); input…

binary verilog modelsim quartus

asked Dec 05 '22 at 01:33

JarvisLYu1

-1

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1 answer

Quartus-FPGA: Disable Path Optimization

module path1(out, in, w0, w1, w2, w3, w4, w5, w6, w7, w8, w9); input in; output out; output w0, w1, w2, w3, w4, w5, w6, w7, w8, w9; not(w0, in); not(w1, w0); not(w2, w1); not(w3, w2); not(w4, w3); not(w5, w4); not(w6, w5); not(w7, w6); not(w8,…

verilog fpga quartus intel-fpga

asked Nov 24 '22 at 11:49

zibidigonzales

-1

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1 answer

How can I prevent that DSP blocks are synthesized away if they are not connected to a top level output?

I am using an Intel Stratix 10 FPGA and Quartus Prime Pro 21.4 to develop a power test project. I cannot figure out how keep Quartus from optimizing away my DSP blocks. I want to use all 3000 DSP blocks in our FPGA so that I can see the max current…

verilog fpga quartus intel-fpga

asked Nov 11 '22 at 12:07

sealenator

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