How can i use generic array type with modelsim?

Question

It's my first question here, I really hope you can help me

Edit 03 December 2019 :

We resolved our problem with the declaration type, but now, we have other problem So, when I tried to run my testbench for the simulation on modelsim, we got these errors.

 # Conv_rev3_run_msim_rtl_vhdl.do 
# invalid command name "Conv_rev3_run_msim_rtl_vhdl.do"

Here our package for the declaration of type

-- synthesis VHDL_INPUT_VERSION VHDL_2008 

library ieee;
use ieee.std_logic_1164.all;

package conv_p is
  type slv_array_t is array (natural range <>) of std_logic_vector;
end package;

The entity of the main files

entity Conv_rev3 is
  generic(
    LEN : natural := 8;   -- Bits in each input
    NUM : natural := 4);  -- Number of inputs
  port(
     clk    : in    std_logic;
     D      : in  conv_p.slv_array_t(0 to NUM - 1)( LEN - 1 downto 0);
     W      : in  conv_p.slv_array_t(0 to NUM - 1)( LEN - 1 downto 0);
    z_o  : out std_logic_vector(LEN*2 - 1 downto 0));
end entity;

Here a sample of our testbench :

    LIBRARY IEEE;                                               
USE ieee.std_logic_1164.all;
USE work.conv_p;                               

ENTITY Conv_rev3_vhd_tst IS
END Conv_rev3_vhd_tst;
ARCHITECTURE Conv_rev3_arch OF Conv_rev3_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL clk : STD_LOGIC;
SIGNAL D : conv_p.slv_array_t(0 to 3)(7 downto 0);
SIGNAL W : conv_p.slv_array_t(0 to 3)(7 downto 0);
SIGNAL z_o : STD_LOGIC_VECTOR(15 DOWNTO 0);
COMPONENT Conv_rev3
    PORT (
    clk : IN STD_LOGIC;
    D : IN conv_p.slv_array_t(0 to 3)(7 downto 0);
    W : IN conv_p.slv_array_t(0 to 3)(7 downto 0);
    z_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
    );
END COMPONENT;

Best Regards

Without a [mcve] and understanding what you did it's not possible from your question title nor the error messages to tell what's wrong. The first error is telling you that a primary unit named conv_p is not found in library work. The second tells us you're likely using constructs introduced in IEEE Std 1076-2008 without telling your VHDL analyzer (compiler, here Modelsim's vcom) that it should use -2008. — , Nov 18 '19 at 22:03
Thank you for your reply "The first error is telling you that a primary unit named conv_p is not found in library work" since we made a file with this unit, we don't understand why it doesn't found it, and the compilation with quartus is working, only the simulation with model sim doesn't work "... telling your VHDL analyzer (compiler, here Modelsim's vcom) that it should use -2008. " We add this "-- synthesis VHDL_INPUT_VERSION VHDL_2008 " on the file where the package is declared We already add "-- synthesis VHDL_INPUT_VERSION VHDL_2008 — Elmatador25, Dec 02 '19 at 12:03
Your [testbench component declaration for ports D and W types don't match the port D and W types in the entity declaration](https://i.stack.imgur.com/SlXnq.jpg). — , Dec 02 '19 at 19:00

score 0 · Answer 1 · answered Nov 20 '19 at 09:58

0

In your first problem, it is highly probable that the entity name that you have specified in your code is wrong and that is why it is unable to find that entity and shows that error. And thus it goes without saying that if it hasn't even found the entity, then it won't be able to compile it. Now I don't think that there is need to answer the second question because there must be some error in it.

answered Nov 20 '19 at 09:58

Kartik Aggarwal

24
5

Thank you for your reply ! We can compile it with alteras quartus, only the simulation on modelsim doesn't work The entity looking for the file with package is the same, We are not sure there is an error (You can check our codes above if you want) – Elmatador25 Dec 02 '19 at 12:06

How can i use generic array type with modelsim?

1 Answers1