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I am designing a FIR filter in Verilog with Quartus II. I need floats for my coefficients so I tried using float however reall is not supported by Quartus so what do I do?

Thanks

George Waller
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  • Can't you use fixed-point arithmetic? – njuffa May 03 '15 at 20:58
  • I guess I can but what data type supports this other than real? – George Waller May 03 '15 at 22:11
  • I don't understand your question. Fixed-point arithmetic basically uses scaled integers, using a scale factor of your choice. Since we are talking about hardware design here, you have complete freedom as to how many integer and how many fractional bits the fixed-point computation is going to use. You could even choose a few different fixed-point representations used in various parts of the computation.The following [write-up](http://www.digitalsignallabs.com/fir.pdf) maybe helpful, but there are other use documents you can find that discuss use of fixed-point arithmetic with FIR filters. – njuffa May 03 '15 at 23:40

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You can't use real, since it is not synthesizeable, follow IEEE-754 format for floating point. can be done by using structural modelling with Altera Megafunctions.

Its recommended to use MAC unit, with floating point options.

check the below link http://quartushelp.altera.com/current/master.htm#mergedProjects/hdl/mega/mega_list_mega_lpm.htm

check for

  1. altfp_mult - multiplier
  2. altfp_add_sub - adder_subtract, configure for adder.

overall floating point arithmetic pdf link https://www.altera.com/en_US/pdfs/literature/ug/ug_altfp_mfug.pdf

ramanathan subramanian
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