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Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also:

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What is multiple constant driver error in VHDL

I am developing a VHDL program for flash interface. While compiling my program I got this error. (clickable) As you can see in the picture, two signals (right hand side) are "xnor" ed and result is assigned to output (flash_oe). Can anyone…
tollin jose
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Verilog - multiple edges in one block like in VHDL?

I'm using Quartus II, version 11.0 and I'm trying to port my VHDL code to Verilog (just for practice). I need to check - how long 'a' line is low. There are working VHDL code: process (clock, a) begin -- on each rising edge of clock... if…
Cluster
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VHDL: Trouble combining entities (components)

Me again! I wrote something SUPER simple in order to demonstrate how entities come together. However, I'm having trouble figuring out why the output of the combined entities never assumes any value (other than U). Here's the code (its super simple,…
Alek988Alek
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VHDL: Why is output delayed so much?

I'm learning VHDL in order to describe and demonstrate the work of a superscalar-ish pipelined CPU with hazard detection and branch prediction, etc. I'm starting small, so for practice I tried making a really simple "calculator" design, like…
Alek988Alek
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Use dma transfert with Cyclone V Avalon-MM for PCIe

Is it possible to do DMA transferts with the IP core «Cyclone V Avalon-MM for PCIe» provided by altera in Qsys (quartus 14.0) ? Altera provide an ip-core named «Cyclone V Avalon-MM DMA for PCIe» to do dma transfert. But this ip-core does not support…
FabienM
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Error (10028): Can't resolve multiple constant drivers for net "sda" at I2C_com.vhd(185)

i'm trying to make my own I2C communication and i have a problem with multiply drivers, it's not like i don't understand them i just don't see them (i'm still fresh at vhdl), so please just take a look at my code and tell mi why is there such…
flanela_man
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Too high results, serial fir filter with DA

I'm trying to make a serial fir filter in VHDL. I used DA to do it. Here is my code: LUT table: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity lut_table is port( x0,x1,x2,x3,x4,x5,x6,x7,x8 : in std_logic; …
Jacob Sokol
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Edit top verilog component generated by Qsys

Is it possible to modify Verilog generated by Qsys before Quartus synthesis ? I designed a component under Qsys. I added the design.qsys file under my Quartus (14.0) project and selected it as «top-level». Qsys generate a verilog top component named…
FabienM
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Code to add two 4-bit integers with verilog doesn't work. What is wrong?

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... module part2(SW, LEDG, LEDR); input [17:0] SW; output [17:0] LEDR; …
OHHH
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Quartus D Flip Flop with asynchronous reset

I need a DFF with asynchronous reset in my diagram. Does quartus have it? If not, how can I implement it?
Feri
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Quartus and modelsim - compile size casting

I'll try to compile in Quartus and simulate in ModelSim some module. See this: module somemodule( ... inputs, outputs, etc... ); localparam BUFFER_LEN = 96; localparam BUFFER_LENW = $clog2(BUFFER_LEN); localparam DATA_WIDTH = 32; logic…
Андрей none
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Why Quartus II recognizes my variable as a signal?

I'm new to VHDL programming, and this is my first project - to build a binary counter with capability for both regular/reverse counting order. My plan is simple: Write a frequency divider process to fetch desired clock frequency and output this new…
Sean Chu
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Combinational loop in a program

There is a error in the program and I'm sure it's caused by negedge iChang in the always block. The error is: Zero-time oscillation in node....... Check the design or vector source file for combinational loop. My partial program is as…
馬宗猷
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Missing EOF at function

I have this VHDL code, it should work as a sine generator with lookup table. I keep getting error "Missing EOF at function", or just "syntax error" in modelsim. I have the syntax from some online tutorial, and it seems to be correct. What is…
MightyPork
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Verilog always block with pushbutton activation, FSM

I'm writing some Verilog code to be programmed on an Altera Cyclone II FPGA board, and I have an always block which should be activated on the press of a key switch: reg START; ... ... always @ (negedge key[3]) begin if (START != 1) START =…
Ryan McClure
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