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I'm studying VHDL right now, and I have a pretty simple homework assignment - I need to build a synchronous BCD counter that will count from 0 to 9 and when it reaches 9, will go back to 0. I wanted to experiment a little so I decided not to do the code in a (at least the way I see it) traditional way (with if, elseif) but with the when-else statement (mostly due to the fact that counter is from 0 to 9 and has to go back to 0 once it hits 9).

library IEEE;
    use IEEE.std_logic_1164.all;

Entity sync_counter is
    port (rst, clk: in std_logic);
end Entity;

Architecture implement of sync_counter is
    signal counter: integer range 0 to 10;
Begin
        counter <=    0 when (rst = '1') else
                      counter + 1 when (clk='1' and clk'event) else
                      0 when (counter = 10);
end Architecture;

So everything compiles, but in the simulation, initially counter jumps from 0 to 2, but after a cycle (0-9 - 0) it is acting normal, meaning counter goes from 0 to 1 as it should be. Same if you force rst = '1'.

Simulation image: BCD Counter simulation

Why does it jump from 0 to 2 in the start?

Thank you.

nettek
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    Post the testbench too. (There is a problem with your code and a good simplification to fix it, but that's unrelated with what you're seeing in this simulation.) The basic approach is valid, if the synthesis tools support it (some may not) –  Mar 28 '15 at 18:57
  • @BrianDrummond I'm not using one. I just compiled the code with Quartus and opened a new project in Modelsim, and added the vhdl file. The signals you see are from using the 'force' function in Modelsim. – nettek Mar 28 '15 at 19:16
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    Then the jump to 2 may be to do with he order in which those commands are being issued, and I can comment no further on that. However for a simpler counter without the asynch race condition, try `counter <= 0 when rst = '1' else counter + 1 mod 10 when rising_edge(clk);` –  Mar 28 '15 at 19:22

1 Answers1

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It may not explain why it goes from 0 to 2. Please post your testbench code on that front. However, your code is bad. This code translate to this, with comments:

process(rst, clk, counter)
begin
    if rst = '1' then -- Asynchronous reset, so far so good
        counter <= 0;
    elsif clk'event and clk = '1' then -- Rising edge, we got an asynchronous flip-flop?
        counter <= counter + 1;
    elsif counter = 10 then -- What is this!?! not an asynchronous reset, not a synchronous reset, not a clock. How does this translate to hardware?
        counter <= 0;
    end if;
end process;

I'm not sure if this would work in hardware, but I can't quickly figure out how it would be implemented, what you want is this:

process(rst, clk)
begin
    if rst = '1' then -- Asynchronous reset
        counter <= 0;
    elsif clk'event and clk = '1' then
        if counter = 9 then -- Synchronous reset
            counter <= 0;
        else
            counter <= counter + 1;
        end if;
    end if;
end process;

I leave the "when-else" statements for purely combinational code, or at most to the single line reg <= value when rising_edge(clk).

Jonathan Drolet
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  • Actually, translates to an equivalent process with a final statement of `wait on rst, clk, counter;` instead of a process sensitivity list. See IEEE Std 1076-2008, 11.6 Concurrent signal assignment statements, paragraph 6 e). And it provides two asynchronous reset conditions which is not a defined form of sequential storage inferring statement, and as you state may not always be synthesis eligible. See IEEE Std 1076.6-2004 (withdrawn), 6.1.3.2 Edge-sensitive storage using a single wait statement. I'd also use your process statement as a fix, this is just detail. –  Mar 28 '15 at 21:28