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So I'm currently trying to synthesize a design and apparently it's too big to compile or something. It compiles and simulates perfectly in ModelSim, but in quartus throws this error:

Error: Design requires 491 I/O resources -- too many to fit in 456 available in the selected device or any device in the device family

Apparently I have 491 I/O resources but can only fit 456 (??). I have no idea what that means or how to extend the 456 number. Google searching gets me nowhere. Does anybody know what to do in this case?

Thanks a lot!

Gaspa79
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  • How do you plan to transfer data to and from FPGA to a computer? 491 pins can not be easily connected to a PC. You should implement or use a IPcore for UART, USB, Ethernet or PCIe. – Paebbels Mar 25 '15 at 01:14
  • @Paebbels: Who said it is (only) communicating with a computer? – Ben Voigt Mar 25 '15 at 03:04
  • I don't plan on doing that. I only want to compile so I can see the circuit synthesized. Can it be done? – Gaspa79 Mar 25 '15 at 04:36
  • Solution 1: You could select a bigger device with more I/O pins (e.g. Stratix 5). Solution 2: Or you could write a wrapper that registera all your outputs and xor's the register values. This reduces the output pincount without giving the compiler the chance to optimize. Solution 3: Generate a netlist - I havn't done that with quartus. – Paebbels Mar 25 '15 at 07:12
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    You are trying to fit a 491 pin design into a package with 456 available pins. Pick a larger package (probably on a larger FPGA). –  Mar 25 '15 at 09:59

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you may try virtual pins assignements:

http://quartushelp.altera.com/13.1/mergedProjects/logicops/logicops/def_virtual_pin.htm

Nicolas Roudel
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