Stack Overflow
Stack Overflow

Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
2
votes
1 answer

ModelSim and SignalTap do not show the same signal level

I do have following signal: signal sl_dac_busy : std_logic := '1'; When I run the ModelSim simulation, the signal level in the reset state shows a High Level while the simulation with SignalTap shows the same signal with a Low Level (also in…
Norick
  • 215
  • 1
  • 8
  • 19
2
votes
1 answer

RTL Viewer Command line

What is the command to run Alter Quartus RTL Viewer, or ModelSim RTL from the Command line under Windows? I tired the following command, however RTL Viewer window does not appear quartus_rpp t -c t --netlist_type=sgate where t is my project's name…
Haskell00
  • 63
  • 1
  • 10
2
votes
1 answer

Modelsim Testbench not generating console output

I've designed a unit for my homework here, module homework1(a, b, sel, y); input signed [7:0] a, b; input [1:0] sel; output reg signed [7:0] y; always @(a or b or sel) begin case (sel) 2'b00: y = a + b; 2'b01: y = a - b; …
Shane Hsu
  • 7,937
  • 6
  • 39
  • 63
2
votes
2 answers

Modelsim change displayed value radix of variables in debug mode

can I change the radix of the displayed value when I'm running with the curser over a variable? So if if hover with my mouse over a variable in debug mode(because a break point was reached) a binary radix is for me not useful. Is there a way to…
alabamajack
  • 642
  • 8
  • 23
2
votes
2 answers

lattice FPGA internal oscillator simulation issues

I'm trying to simulate ICE5LP1K FPGA internal oscillator on ModelSim. My design includes the following instance: SB_HFOSC OSCInst1 ( .CLKHFEN(1'b1), .CLKHFPU(1'b1), .CLKHF(CLKLF) ) I included sb_ice_syn.v file but have a design loading…
Tigran
  • 41
  • 3
2
votes
1 answer

a few issues about 'tri' data type in SystemVerilog

I just started to use the 'tri' datatype these days. And I've applied this datatype in two different modules. It serves the first module nicely in terms of logic and structural simulation (before synthesis), where basically I have a bunch of logic…
Tidus
  • 37
  • 2
  • 9
2
votes
2 answers

variable-sized parameter array in verilog

I am observing odd behaviour when simulating a design with a parameter array in (system)verilog. Here is my module interface: module src_multi #( parameter NUM_DEST = 4, parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1]…
mohsaied
  • 2,066
  • 1
  • 14
  • 25
2
votes
1 answer

Jump from breakpoint to breakpoint in ModelSim

Is there a way to jump from breakpoint to breakpoint while debugging any design (VHDL or Verilog entry) in ModelSim ?
shrm
  • 1,112
  • 2
  • 8
  • 20
2
votes
2 answers

ModelSim: using a silent stop command inside 'when' block

I am trying to get a ModelSim simulation to stop when a particular event occurs, or after a timeout, whichever comes first. I have tried a purely software approach, using a while loop and issuing a run 1 ns command at every iteration and checking if…
user955279
2
votes
1 answer

How to fix error "Can't resolve indexed name"

I Write and decelerate this code in Modelsim but in my component i will get error "Can't resolve indexed name type std_ulogic as type std_logic_vector". how to fix it? library IEEE; use ieee.std_logic_1164.all,ieee.numeric_std.all,Work.all; entity…
Mohammad Sadeghi
  • 23
  • 1
  • 7
2
votes
1 answer

Global declarations are illegal in Verilog 2001 syntax!

I have written something small in verilog: `define LW 6'b100011 `define SW 6'b101011 parameter [3:0] i_fetch = 4'b0001, decode_rr = 4'b0010, mem_addr = 4'b0100, alu_exec = 4'b1000; and i am getting this error: Error: test.v(5):…
Kostas
  • 1,319
  • 12
  • 18
2
votes
1 answer

what is the solution of Error in TCl script?

I recently downloaded Modelsim 10.1 from altera.com and i am getting this message of "Error in TCL script". I am not able to start a new verilog project. Here is the error Trace back: can't read "Project(SaveCompileReport)": no such element in…
rahuldce
  • 51
  • 1
  • 2
2
votes
1 answer

Is there a way to assert that all signals in a design are initialized on rising clock during reset?

Just from the tester flow (no changes to design) is there a quick way to assert that all the design signals are initialized during reset? Design uses synchronous active low reset. On the rising edge of reset I want to assert that every signal in the…
user2449111
2
votes
2 answers

UVM_INFO returning a HEX value

I use this command to print the contents of the transaction class in Questasim: `uvm_info("VALUES", tx.sprint(), UVM_LOW) My transaction has a variable ans. The problem is it is printing it as HEX rather than DECIMAL. It shows: ans integral …
Vineeth
  • 111
  • 2
  • 11
2
votes
1 answer

How can I make Modelsim warn me about 'X' signal?

I am working on large design using Modelsim. I've read about the way modelsim simulation works. I am wondering, is there a way that when modelsim evaluates a signal in the simulation phase and it found it to be a red signal, i.e. 'X', to warn me…
Ma Eb
  • 21
  • 1
1 2 3
…
50 51