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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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The input and output signals are not shown in objects windows in Modelsim10.1c

I am a beginner in designing circuit using verilog in modelsim. I use a sample code and a tutorial to learn how modelsim works. The code and the testbench are compiled without any problem and even testbench is simulated without any error but the…
abolfazl taghribi
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Suppress Specific IP Warnings in Modelsim

A Vivado IP is generating an inordinate amount of Modelsim warnings which are making it difficult to assess the simulation for warnings I actually care about. I see from the Modelsim command documentation that in order to suppress a warning I need…
Marmstrong
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How to pass an array type as generic type parameter to a VHDL package?

I'm working on a generic package (list) in VHDL-2008. This package has a type generic for the element type. If I declare an array type of this element type within the package, it's a new type. So for e.g. integer, my new integer_array would be…
Paebbels
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How run Modelsim with vsim command in terminal?

Now I'm can run it with ./vsim command from folder /quartus/modelsim_ase/linuxaloem when I'm put vsim, get No command 'vsim' found, did you mean: ... but when I'm try run leon3 simulation from grlib via make vsim-launch I'm get /bin/sh: 1: vsim:…
stack user
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Module not Defined When Simulating Using Modelsim

So I've upgraded from Vivado 2015.4 to 2016.2. I use Vivado to compile the simulation files for the encrypted IPs. When I launch Modelsim 10.4, a new error appears: sources_1/ip/output_buffer/sim/output_buffer.v(289): Module 'fifo_generator_v13_1_1'…
fiz
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VHDL : for loop, index arithmetic doesn't work

I'm trying to set up a simple bruteforce convolution processor with my DE0 Nano Altera FPGA board. Here's what my code looks like : LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_bit.all; ENTITY Convolution IS PORT( clock : IN…
ricothebrol
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Quit Modelsim from command line on error

I am using a .do file which is used by GUI and by .tcl in command line (vsim -c) for simulating in Modelsim 10.3c exec vsim -c -do DoFile.do What I need is: If an error happens, modelsim should be quit and return to the .tcl. Otherwise it should…
Stingray
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How to set the value of a macro using environment variable or command line in verilog?

I want to define a macro during runtime in Verilog using environment variable. For example, I want to print some text to a file only when the DEBUG macro is defined as 1. `define DEBUG 0 ... if(DEBUG) $fwrite(file,"Debug message"); How can I…
Shafeey
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in vhdl case statements,how to deal with 4 value logic?

I am a newer to vhdl, and I'm working for a project. but something block me recently: if reset='0' then prstate<="00"; else if rising_edge(clock) then case prstate is when "00"=> if wd_link='1' …
user6455551
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Using a variable in more than one funciton?

it is probably because of me being newbe. Anyways, I want to define some variables to use in more than one function (like global variables in C). I decided to go with shared variables but it gives me the error Cannot reference shared variable "x"…
ismylhakkituran
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modelsim script on start up

I run ModelSim (Altera 13.1 SE) and I want following: 1. Load file tb.wlf 2. Add all signals to wave I do this: vsim tb.wlf -do "add wave -r /*" or vsim -do "vsim tb.wlf;add wave -r /*". Modelsim reads all script, loads signals from tb.wlf but…
Victor Akhlynin
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Verilog Array Assignment

So I am trying to assign numbers to an array in verilog, and it goes like this: initial begin waveforms[0] = 16'b1100100100000000; waveforms[1] = 16'b1000000000000000; waveforms[2] = 16'b1111111111111111; end And the following codes can pass…
Tony
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How do I specify the time resolution in Cocotb?

I am getting a different clock period, when I am simulating the Endian Swapper example of Cocotb in VHDL and Verilog mode using QuestaSim. The clock is generated in the same way for both modes in the provided example code: @cocotb.coroutine def…
Martin Zabel
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VHDL: Indexing in component port map

comp_A1: comp_A port map ( CLK => CLK, RESET_N => RESET_N, DATA_IN => DATA(to_integer(unsigned(count))), VLD_IN => VLD_IN, …
rkshthrmsh
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Does not work as before Verilog initial construction in ModelSim Altera Edition 10.4

Since version 10.4, start problem with initial block. Like this: reg [31:0] init_ram[15:0]; initial begin init_ram[0] = 32'h1234_5678; init_ram[1] = 32'h8765_4321; ... end always_ff @(posedge clk) init_ram[addr] <= data; Or module…
Papayaved
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