Is there a way to assert that all signals in a design are initialized on rising clock during reset?

Question

Just from the tester flow (no changes to design) is there a quick way to assert that all the design signals are initialized during reset?

Design uses synchronous active low reset.

On the rising edge of reset I want to assert that every signal in the design is not 'U' without having to call out each signal or architecture.

Using VHDL 2008, Modelsim 10.1c with HDL Designer.

Could you give an example of the code that is concerning you? It's not clear if you're concerned about the reset not arriving properly, or if you want to be able to have an implicit reset. — Bill Lynch, Oct 17 '14 at 16:50
In VHDL a design specification is comprised of design units (including a PSL Verification Unit - IEEE Std 1076-2008). The elaboration of a a design hierarchy is a prelude step to simulation, and the scope and visibility rules limit access to named entities. Further there is no way to limit the scope of the suffix `all` to particular named entity classes. These imply there is no VHDL language way to inspect every signal in an elaborated design with an assertion or PSL declaration without specifying it directly. I added the modelsim tag to try and attract more tool answers. — , Oct 17 '14 at 20:40

score 2 · Answer 1 · edited May 23 '17 at 11:52

You can adapt the use of the Modelsim when command from this answer to look for 'U' in any signals after the synchronous reset is released. As it exists it works with scalars and arrays but cannot examine record members.

Note that the rising edge of reset is not the time that reset is released since you are using synchronous reset. I would make the test wait for the first falling edge of clock when reset is high to test for 'U'. This will ensure that you see the new state on signals when their drivers update after the reset. The when expression would be something like:

"clk'event and clk = '0' and reset = '1' and $sig = [string repeat U [string length [examine $sig]]]"

Another option would be to create a sentinel signal in the testbench that evaluates to true when reset is released and test for that in the when expression:

signal reset_inactive : boolean;

process(clk) is
begin
  if rising_edge(clk) then
    if reset = '1' then
      reset_inactive <= true;
    else
      reset_inactive <= false;
    end if;
  end if;
end process;

...
When expression:
"reset_inactive'event and reset_inactive = true and $sig = ..."

Once complete it would be a good idea to cancel the waits with the nowait command to avoid the performance hit of having a wait on every signal in the design since you only need this test after reset.

Is there a way to assert that all signals in a design are initialized on rising clock during reset?

1 Answers1