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I Write and decelerate this code in Modelsim but in my component i will get error "Can't resolve indexed name type std_ulogic as type std_logic_vector". how to fix it?

library IEEE;
use ieee.std_logic_1164.all,ieee.numeric_std.all,Work.all;

entity NbitCarrySkipAdder is
generic (n: integer :=8);           
Port(A, B: in  std_logic_vector (n-1 downto 0);
    Cin:  in std_logic;
    Sum: out  std_logic_vector (n-1 downto 0);
    Cout: out std_logic);
end NbitCarrySkipAdder;

architecture behavioral of NbitCarrySkipAdder is

  component NBitBlockWithSkipAdder is 
  generic(n:integer:=4);
  port( a, b : in std_logic_vector( n-1 downto 0);
        Cin_Block : in std_logic;
        S : out std_logic_vector( n-1 downto 0);                        
        Cout_Block : out std_logic);
end component NBitBlockWithSkipAdder;
signal Carry: std_logic_vector(0 to n);
begin

g1: for i in 0 to n-1 generate

lt: if i = 0 generate
       f0: NBitBlockWithSkipAdder port map (A(i),B(i),Cin,Sum(i),Carry(i+1));
     end generate lt;

rt: if i = n-1 generate
       fn: NBitBlockWithSkipAdder port map (A(i),B(i),Carry(i),Sum(i),Cout);
     end generate rt;

md: if i > 0 and i < n-1 generate
       fm: NBitBlockWithSkipAdder port map (A(i),B(i),Carry(i),Sum(i),Carry(i+1));
     end generate md;
end generate g1;

end architecture behavioral;

deceleration of my component is same as deceleration in the above code. thx

Mohammad Sadeghi
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1 Answers1

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Problem is that A(i) is a std_logic in port map for NBitBlockWithSkipAdder, but a port is declared as std_logic_vector.

Either change the port type in NBitBlockWithSkipAdder to std_logic, or use a range of one element in A in order to get a std_logic_vector with a single bit, like A(i downto i), thus making instantiations like:

f0 : NBitBlockWithSkipAdder port map (A(i downto i), B(i downto i), Cin, Sum(i downto i), Carry(i+1));
Morten Zilmer
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