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I do have following signal:

signal sl_dac_busy      : std_logic := '1';

When I run the ModelSim simulation, the signal level in the reset state shows a High Level while the simulation with SignalTap shows the same signal with a Low Level (also in the reset state).

What could be possible reasons for the different signal level? Do I need to set an (additional) initial value for this signal or...?

Thanks!

EML
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Norick
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  • Assigning signal values is only supported for registers and if synthesis if run for FPGAs. Otherwise use a constant or an assignment in the architecture body. – Paebbels Jan 07 '16 at 09:43
  • I have corrected my answer because the actual cause is another one. I have seen this inverted behaviour also in my designs, but didn't investigated it thoroughly until now. – Martin Zabel Jan 10 '16 at 18:04

1 Answers1

3

After discussion with Russel in the comments, I found out, that some points in my original and accepted answer were wrong. Of course, Quartus-II supports an initial high value for flip-flops after power-up, but, the actual mapping on Altera FPGAs causes a difference between ModelSim and SignalTap.

The programmable flip-flops on all Altera FPGAs (as of 2016) can only by initialized to zero as stated in the Quartus Prime Pro Edition Handbook Volume 1: Design and Synthesis in Section 11 "Recommended HDL Coding Styles":

Registers in the device core always power up to a low (0) logic level on all Altera devices.

An initial value of high (1) logic level is emulated on Altera FPGAs by inverting the flip-flop (FF) data input and output and then initializing the FF to low instead of high as also described in the Section 11. Thus, the description of this FF:

library ieee;
use ieee.std_logic_1164.all;
entity FF_init1 is
port (D, CLK : in  std_logic;
      Q      : out std_logic);
end FF_init1;
architecture rtl of FF_init1 is
  signal FF : std_logic := '1';
begin
  FF <= D when rising_edge(CLK);
  Q  <= FF;
end rtl;

will be mapped like this:

mapping

Don't overlook the inverter on the D input of the FF. After power-up the FF itself is initialized to low, but due the negation of the Q output afterwars, it behaves as an initialization to high of the output Q of the entity FF_init1. During run-time, the FF stores the negated input at the rising clock-edge, which is again negated at the output.

The inverter at the output might be merged into the subsequent logic, so that, you cannot always connect SignalTap after the output inverter. Often, you can only connect SignalTap to the FF output itself, but this wire has an opposite logic level to the signal value of FF within ModelSim.

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Martin Zabel
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  • Just a comment to your Verilog comment above... those init values you're assigning are not only used in simulation. Those are used by the bitstream to initialize your FPGA to a known state, which is very handy when programming your FPGA. – Russell Jan 08 '16 at 13:33
  • @Russell I didn't write anything about Verilog. No, Quartus-II ignores initial values for VHDL signals because the flip-flops on Altera FPGAs (!) are always initialized to zero upon power-up. In contrast to this, the flip-flops on Xilinx FPGAs also support a power-up to one. – Martin Zabel Jan 08 '16 at 13:47
  • you're right, I meant VHDL, not Verilog... but I'm pretty sure you're mistaken about the Altera FPGAs always initalized to zero on power up. As far as I know, all LUT-based FPGAs can be initialized by the bitstream. Can you point me to some Altera literature stating otherwise? – Russell Jan 08 '16 at 14:30
  • @Russell Take a look in this [Cyclone 5 Datasheet](https://documentation.altera.com/#/00088891-NT$NT00064904). If this link does not work, navigate to the Cyclone 5 Datasheet on the Altera website and enter the search term "register power-up". The mentioned NOT-gate push back is only applied to support asynchronous set. – Martin Zabel Jan 08 '16 at 14:39
  • After reading the literature, it appears that I was wrong with the actual process of how registers are initialized. I assumed that the bitstream was able to initialize all the registers to a non-zero state, but that's not how Altera does it. They do their NOT gate push-back thing, which is for all intents and purposes achieves the same thing. So you can still safely initialize non-zero values in an Altera FPGA, it's just a bit more complicated than doing it on Lattice or Xilinx FPGAs. – Russell Jan 08 '16 at 14:56
  • @Russell I have corrected my answer. I have seen this inverted behaviour also in my designs, but didn't investigated it thoroughly until now. – Martin Zabel Jan 10 '16 at 18:03
  • Thanks for updating your answer! I learned a lot from this post! – Russell Jan 11 '16 at 14:24