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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

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Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)

In ModelSim you can use something like in modelsim we can use init_signal_spy("../.../sig", mysignal); to get deep hierarchy signals. Is there a way to get such signals with Cadence's NCVhdl? This should be flagged "SimVision", which is the name the…
Sadık
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Is there a way to print the values of a signal to a file from a modelsim simulation?

I need to get the values of several signals to check them against the simulation (the simulation is in Matlab). There are many values, and I want to get them in a file so that I could run it in a script and avoid copying the values by hand. Is there…
SIMEL
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Verilog-A & Verilog ; Are they the same?

Is Verilog-A the same as Verilog ? Is there a testing compiler for Verilog-A? Because when I just paste some sources code of Verilog-A on ModelSim, there are always some errors that can't be removed. Can ModelSim run Verilog-A?
user3625354
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Using the VHDL 2008 generic type feature to create pseudo-dynamic types

I'm trying to create a record that can hold data of different types, would that be possible in some way using VDHL 2008's generic typing feature? I'm not trying to synthesize that code. My test setup looks like this: library ieee; use…
youR.Fate
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VHDL: Unable to read output status

I'm attempting to compile in ModelSim 10.0 and I receive a compile error stating: 'Cannot read output status'. Here's a snippet of the code. It'd be brilliant if someone could tell me what I'm doing wrong. entity controller_entity is generic(…
SeanTheStudent
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ModelSim Compiler not the same as Quartus

I was using ModelSim to do the simulation these days, and a problem came to me, that is: And thers was a piece of verilog code like this: if (cnt == `END_CNT) ... reg [7:0] cnt; always @(posedge clk) if (en) cnt <= cnt +1; ... which…
Mr.Zhou
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Does ModelSim support program blocks?

When running the following trivial code with ModelSim 10.1d program test; initial begin $display("hello world"); end endprogram I'm seeing Error loading design. The issue can be reproduced here: http://www.edaplayground.com/s/4/807 I know…
Victor Lyuboslavsky
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display a real in verilog but bitstoreal returning only 0.000000

I am trying to display a real number during the simulation of my verilog code in modelsim. But I only get 0 as output. I am trying to use the bitstoreal system function. I'm not so good at verilog so it could be a stupid beginner's…
Moberg
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How to simulate an Altera megafunction using Modelsim SE

___Hi, everyone. I have instantiated a PLL using the Megawizard in Quartus II. Then I wanted to simulate it using ModelSim SE because Quartus II 10.1 doesn't have a built-in simulator. I copied builtInPLL.vhd (output of the Megawizard) and…
sensor
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Is a <= a + 1 a good practice in VHDL?

If I write the statement to assign a to be a+1 in a VHDL process, is it a good practice? I am confused about this because the simulator works fine, but when I try to implement it in FPGA the synthesis tool complains about creating latches. What does…
Bob Fang
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VHDL wait on multiple signal

signal a:bit:='1'; signal b:bit:='0'; signal c:bit:='0'; begin process variable d:bit:='0'; begin if (a='1')or(b='0') then a <= inertial not d after 1ns; else a<=inertial not c after 1.5ns; end if; d := a and b; b <= inertial…
JanBo
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How to represent array literals in VHDL?

I have the following type declarations: type cachesubset is record tag : std_logic_vector(3 downto 0); word0 : w32; word1 : w32; dirty : std_logic; …
Andry
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Conversion function "To_bit" must have exactly one formal parameter

I am getting above error while running modelsim on a VHDL Testcase and I am unable to understand why is it an error. The Testcase: LIBRARY IEEE; Use ieee.std_logic_1164.all; entity a is port (in11 : in std_logic ); end a; Architecture a of a…
Dharmendra
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Tcl binary loop. Binary increment

I am trying to write a tcl script for my decoder module (verilog in modelsim) I need to loop the 'din' input value from from 000 to 111 Thats what i've come up with by now. vsim work.decode_shift add wave -noupdate -format Logic -radix binary …
user1405165
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Verilog I/O reading a character

I seem to have some issues anytime I try anything with I/O for verilog. Modelsim either throws function not supported for certain functions or does nothing at all. I simply need to read a file character by character and send each bit through the…
kdgwill
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