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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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Passing C structs through SystemVerilog DPI-C layer

SystemVerilog LRM has some examples that show how to pass structs in SystemVerilog to\from C through DPI-C layer. However when I try my own example it seems to not work at all in Incisive or Vivado simulator (it does work in ModelSim). I wanted to…
user3716072
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System Verilog Bus Routing

In system verilog, I know you can route a partial bus with array[15:8] as a way to split lanes. Is there any way to do this in a non continuous way. For example, lane 2,3,8,9 .
Ryu
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With ModelSim, how to update waveforms to the newest dataset?

Background : ModelSim v10.4d installed with quartus v16.0 I wrote a .do file to simulate my design with ModelSim. The steps in my .do file are: 1- vcom *.vhd : compile all sources files and testbench 2- vsim work.my_tb : load testbench for…
Cong Li
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Why does Modelsim 10 not compile older code?

I just recently upgraded to Modelsim 10 and when I recompiled all my code, only 30 out of 37 compiled. Those that wouldn't compile had a common error No feasible entries for infix operator "&" I simply included the packages for std_logic, change…
sj755
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How can I undo something set in the global modelsim.ini?

I want to use OSVVM. Modelsim comes with an older version of OSVVM precompiled in a library called osvvm. This is set up in the global modelsim.ini file: osvvm = $MODEL_TECH/../osvvm I would like to be able to compile a later version of OSVVM. I…
Matthew Taylor
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Adding two bit_vector in VHDL return error "(vcom-1581) No feasible entries for infix operator '+'."

This is my code for converting binary to BCD in VHDL library ieee; use ieee.numeric_bit.all; entity bin2bcd is port (bin : in bit_vector(3 downto 0) := "0000"; clk : in bit; bcdout : out bit_vector(4 downto 0) := "00000"); end…
Siladittya
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Using configuration specification in VHDL/ModelSim

I'm trying to use a VHDL configuration specification to pre-set This should be possible, as shown in IEEE1076-2008, section 7.3.2.1, which gives the following example: entity AND_GATE is generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); port…
JHBonarius
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modelsim says : "near ")": (vcom-1576) expecting IDENTIFIER." while compiling

I just wrote this : library ieee; use ieee.std_logic_1164.all; entity and_gate is port( input_1 : in std_logic; input_2 : in std_logic; and_result : out std_logic; ); end and_gate; architecture rtl of and_gate is signal and_gate :…
Muhammadreza
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Parallel CRC CCITT 16 Kermit in VHDL

I am trying to implement CCITT 16 true type (Kermit) in VHDL language. Here are the parameters: width=16 poly=0x1021 init=0x0000 refin=true refout=true xorout=0x0000 check=0x2189 residue=0x0000 name="KERMIT" I have 32-bit data and want to generate…
Gaurav Bhatia
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Passing a struct as a parameter in System Verilog

The following code works fine under Modelsim when the unused localparam is removed. It produces the error below if it is left in. If it is possible to use a struct to pass parameters to a module, what am I doing wrong? Many thanks. typedef bit [7:0]…
jeremiah
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ModelSim on Ubuntu

I just installed the latest version of ModelSim on Ubuntu 16.04.1. But I can't launch the software by using this command ./vsim. It always said bash: ./vsim: No such file or directory Can anybody help? Thanks.
S. Li
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modelsim verilog vsim-3365 too many port

// Dataflow description of a 4-bit comparator module FourBcompare ( output A_lt_B, A_eq_B, A_gt_B, input [3: 0] A, B ); assign A_lt_B = (A < B); assign A_gt_B = (A > B); assign A_eq_B = (A ==…
raon kim
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How do I bind different component instantations (in testbench) to different architectures in VHDL?

I create a multiplexer called mux21_generic.vhdl. It is a Nx1 mux. I define two architectures, one behavioral, the other structural. The structural architecture uses a small 2x1 mux in the following way: architecture structural of MUX21_GENERIC…
igol
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How to add compile option for ModelSim using VUnit?

Using ModelSim and VUnit I try to compile some UVVM, but this gives some warnings like: ** Warning: C:\work\Qtec\SVN_sim\Design\uvvm\uvvm_util\src\methods_pkg.vhd(1159): (vcom-1346) Default expression of interface object is not globally static. So…
EquipDev
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VHDL constant array case choice

I have the following declaration in my architecture: architecture behavioral of my_widget is type register_bank_t is array(1 to 4) of std_logic_vector(31 downto 0); -- register addresses constant address : register_bank_t := ( …
aghoras
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