How do I bind different component instantations (in testbench) to different architectures in VHDL?

Question

I create a multiplexer called mux21_generic.vhdl. It is a Nx1 mux. I define two architectures, one behavioral, the other structural.

The structural architecture uses a small 2x1 mux in the following way:

architecture structural of MUX21_GENERIC is

component MUX21 is
    Port (  A:      In      std_logic;
            B:      In      std_logic;
            S:      In      std_logic;
            Y:      Out     std_logic);
end component MUX21;

begin  -- structural

    create_mux:
        for i in 0 to N-1 generate
        begin
            MUX21_i : MUX21 port map(A=>A(i), B=>B(i), S=>SEL, Y=>Y(i));
        end generate create_mux;

end structural;

These are the configurations:

-- CONFIGURATIONS --

-- (1) CFG_MUX21_GEN_BEHAVIORAL

configuration CFG_MUX21_GEN_BEHAVIORAL of MUX21_GENERIC is
    for behavioral            
    end for;
end CFG_MUX21_GEN_BEHAVIORAL;

-- (2) CFG_MUX21_GEN_STRUCTURAL

configuration CFG_MUX21_GEN_STRUCTURAL of MUX21_GENERIC is
    for structural
        for create_mux
            for all : MUX21
                use configuration WORK.CFG_MUX21_STRUCTURAL;
            end for;
        end for;
     end for;        
end CFG_MUX21_GEN_STRUCTURAL;

The compilation works well, so I don't think the problem is in the above configurations.

I guess the problem is in the testbench.

The following code represents how I instantiate, in the "TEST" architecture of the testbench, both the behavioral and the structural mux:

U1 : MUX21_GENERIC
Generic Map (NBIT, 7 ns) 
Port Map ( A1, B1, S1, output_beh); -- it should be behavioral 

U2 : MUX21_GENERIC
Generic Map (NBIT)
Port Map ( A1, B1, S1, output_str); -- it should be structural

and this is the configuration that I wrote in the testbench:

configuration MUX21GENTEST of TB_MUX21_GENERIC is
   for TEST

      for U1: MUX21_GENERIC
          use configuration WORK.CFG_MUX21_GEN_BEHAVIORAL; 
      end for;

      for U2: MUX21_GENERIC
          use configuration WORK.CFG_MUX21_GEN_STRUCTURAL; 
      end for;

    end for;
end MUX21GENTEST;

Now the problem is that when I start the simulation with modelsim, It instantiates both the component with the structural architecture. Modelsim image

I notice that if I exchange the position between the two architectures in the mux21_generic.vhdl file, modelsim uses the behavioral instead of the structural arch. Should it be a configuration problem?

score 1 · Answer 1 · answered Apr 01 '17 at 21:49

You don't provide a Minimal, Complete and Verifiable example.

Your configurations are overly complex.

In your testbench configuration you could:

configuration MUX21GENTEST of TB_MUX21_GENERIC is
   for TEST

      for U1: MUX21_GENERIC
          use entity WORK.MUX21_GENERIC(behavioral); 
      end for;

      for U2: MUX21_GENERIC
          use entity WORK.MUX21_GENERIC(structural);
      end for;

    end for;
end MUX21GENTEST;

Without relying on superfluous configurations. There's a concept in VHDL called binding indication where the default binding indication can be supplanted by a configuration specification (which can be found configuration declarations or as block declarative items).

When your configuration declaration(s) appear to ignore specific binding indications and use the default it's because they aren't applicable. (The component binding indication is invalid).

Using configuration specifications in your testbench without a configuration declaration entails providing them as architecture declarative items.

Without an MCVe providing an answer entails a certain amount of risk due to uncertainty from lack of visibility and the inability to test a solution without replicating your work.

How do I bind different component instantations (in testbench) to different architectures in VHDL?

1 Answers1