2

I just wrote this : 

library ieee; 
use ieee.std_logic_1164.all; 

entity and_gate is
 port(
  input_1 : in std_logic; 
  input_2 : in std_logic;
  and_result  : out std_logic;
 );
end and_gate; 

architecture rtl of and_gate is
 signal and_gate : std_logic; 
 begin 
  and_gate <= input_1 and input_2; 
  and_result <= and_gate; 
 end rtl;

And when I compile it, the modelsim compiler gives me this error : 

** Error: C:/modeltech64_10.5/examples/and_gate.vhd(8): near ")": (vcom-1576) expecting IDENTIFIER.

I searched and tried some solutions, but I still get errors.

Muhammadreza
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1 Answers1

5

This

and_result  : out std_logic;

should be this

and_result  : out std_logic
Matthew Taylor
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