VUnit is a unit testing framework for VHDL/SystemVerilog.
More information at VUnit.
Questions tagged [vunit]
11 questions
5
votes
1 answer
How to combine multiple VUnit run.py files into a single VUnit run?
I have a directory and file structure like this:
vunit_multi/
alfa/
run.py
...
bravo/
run.py
...
The VUnit run.py can run separately.
Is there any nice way to combine these multiple separate VUnit runs into a…
EquipDev
- 5,573
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2
votes
1 answer
Can I control the execution order of VUnit testbenches?
I have several VUnit unit testbenches and a single top level testbench in my design projects. VUnit finds all my testbenches and executes them. I would like to control the order the testbenches are executed, so I can have the shorter testbenches…
Locksley Haynes
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- 3
2
votes
1 answer
How to add compile option for ModelSim using VUnit?
Using ModelSim and VUnit I try to compile some UVVM, but this gives some warnings like:
** Warning: C:\work\Qtec\SVN_sim\Design\uvvm\uvvm_util\src\methods_pkg.vhd(1159): (vcom-1346) Default expression of interface object is not globally static.
So…
EquipDev
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1
vote
1 answer
vunit, what are reset conditions between test case
I'm very confused about vunit testing, especially the link between tests and the way they are reset.
Please take a look at next minimal example:
device under test
Device has one inner state that latch on 1 when input goes to 1
library IEEE;
use…
NRagot
- 113
- 2
- 12
1
vote
1 answer
Test for Assertion Failure in VUnit
I may have some functions that assert and fail if they're not happy.
How do I test this functionality with VUnit to ensure that these functions do in-fact throw the failure in the right conditions?
For instance, lets say I wanted to check this…
ScottishTapWater
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1
vote
1 answer
Is it possible to have VUNIT run a test suite based on top level generics?
I am new to Vunit - but not testing. I currently have a setup where I have testbenches that use a lot of OSVVM where setup is provided via generics to the testbench, and I use either TCL or Pytest to run the test through a full test suite.
Having…
Tricky
- 3,791
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1
vote
1 answer
how to use VUnit on a system level
I have a project with multiple structural entities that each have sub-entities like the picture below.
Now I am trying to plan for the testing phase. I have checked UVVM, OSVVM, and VUnit and I found that VUnit is the easiest and fastest way to…
Ahmad Zaklouta
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1
vote
1 answer
Run same testbench with different parameter files in VUnit
I have a project with the following structure:
tb_top
├── run.py
└── src
├── tb_top.vhd
├── test_a
│ ├── top_parameter.vhd
│ ├── input.csv
│ └── output.csv
├── test_b
│ ├── top_parameter.vhd
│ ├── input.csv
…
Marph
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1
vote
1 answer
Is there a workaround for the data_width limitation (32 bit) in vunit_lib.array_pkg
I have the array_axis_vcs VUNIT example running.
Now I want to customize the example to my needs, a.o. increasing the data_width size (32 bit in the example).
Doing this, the error below appears.
It seems there is a limitation to 32 bit for the…
Marcus
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- 1
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1
vote
1 answer
VUnit: ERROR - Cannot add library named work using `udp_ip_stack-master`
Wanted to try out VUnit, thus followed the Getting Started 1-2-3.
For blog 1, I installed Python ver. 3.6 and using ModelSim ver. 10.5a.
For blog 2, I downloaded example project udp_ip_stack-master.zip example project, but when I run:
python…
EquipDev
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0
votes
2 answers
VUnit test sequential components
How to test sequential components properly with VUnit testing library and using VHDL? I've been using it to test combinatorial components using wait for statements etc. Example of it here in my github repo.
Obviously I've to generate a clock signal…
Kazooie
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