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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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Issue with reading bus signal. Compare to my Modelsim DE 10.2c and 10.4. EDAplayground Modelsim 10.1d has different result

Hi any SystemVerilog experts with Mentor Graphic Modelsim Tool. I am writing a monitor task to process a simple PCI single word write/read bus event. Somehow EDAplayground Altera Modelsim 10.1d requires extra clock cycle for unknown reason while…
Michael Li
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VHDL n-bit barrel shifter

I have a 32 bit barrel shifter using behavior architecture. Now I need to convert it to an n-bit shifter. The problem that I'm facing is that there is some kind of restriction to the for loop that I have to put a constant as sentinel value.…
faizan ali
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Types unmatch VHDL code at Simulation on Modelsim, inspite of thorough check

I am requesting some help because I am completly stuck in my VHDL project, consisting in implementing a cartesian to polar convertor on Nios II. All of my VHD files do compile without error, but when I want to simulate the whole block on Modelsim,…
koudi sidi
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Verilog Continuous Simulation

Are there special start and end keywords in verilog that will allow a simulation to continue running until an end keyword is met? I understand this would not be synthesizable; however, I only wish to use it for testing purposes. Also the $finish…
kdgwill
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Simulation mismatch when using shortreal + shortrealtobits + bitstoshortreal combination in modelsim tool

Here is the minimal reproducible problem: file: top.sv module top(input [31:0] in1, output [31:0] out1); assign out1 = in1; endmodule file top_tb.sv module top_tb; shortreal in1_real; shortreal out1_tb; shortreal out_dut; logic [31:0]…
Rajkumar Ananthu
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How to correct this error "Illegal reference to net q"?

I am getting this error when I am compiling my file which Using Behaviour Modelling is designing a positive edge triggered T-Flip-Flop with asynchronous clear in Verilog code. module t_flip_flop (input clk, input pr, input clr, input d, output q); …
Sai Ganesh K
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Error near "output": syntax error, unexpected output, expecting ')'

module rc_adder4 ( input logic[2:0]a, b output logic[2:0] s, output logic c_out ); logic [3:0] c; rc_adder_slice UUT[2:0] ( .a(a), .b(b), .c_in(c[2:0]), .s(s), .c_out(c[3:1]) ); // COMPLETE USING ARRAY…
Valerie Wang
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Unable to compile Micron's DDR3 memory model in Modelsim

I downloaded the memory model for the DDR3 bank that I'd be testing in simulation using Modelsim (2019.2) from Micron's website (link). I followed the instructions from the README file to compile it, but I ran into syntax errors. I don't think…
surabhig
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How to instantiate a component that takes a generic package?

I have the following situation: I have modules X and Y in my VHDL design which can be customized according to a large set of parameters. For that, I include these parameters as Generics that are part of the declarations of X and Y. Moreover, X must…
mbrandalero
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How to make this VHDL 'for' loop work with no error on modelsim?

I have a 'for' loop in my VHDL design that gives an error on modelsim : "Illegal concurrent statement". My VHDL architecture is a few hundreds lines long so I will just show what gives an error : for k in 0 to 19 loop DATA_SERDES(k) <=…
SLP
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Modelsim Error: No objects found matching '/test/*'

I am a newbie to modelsim and Verilog. I designed a DFF(D flip flop module) and a test bench for testing it. But I can't get why modelsim give me this error: No objects found matching '/test/*' test bench code: // Testbench module test; …
user9810241
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What is the advantage of using a testbench rather than a ".do" file in ModelSim?

What is the advantage of using a testbench rather than a ".do" file in ModelSim? A ".do" file allows me to force and examine ports. The testbench seems to do exactly the same thing. So why use a testbench and not a ".do" file? Thank you!
Tal J
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How to access VHDL signal attributes in ModelSim via TCL?

I am developing a CPU in VHDL. I am using ModelSim for simulation and testing. In the simulation script I load a program from a binary file to the instruction memory. Now I want to automatically check if the program fits into memory and abort…
programonkey
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How to modify initialization done by modelsim?

My question is related to the initialization done by modelsim. I want to use integer in a particular range (range 0 to 511 for example). Here is the declaration in VHDL: signal cnt : natural range 0 to 511; If I do not initialize this signal (in…
Matthieu
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hierarchical compile order with modelsim on command line

I'm trying to compile a VHDL design with modelsim on command line. Is there any way to get an automatical compile order according to the design hierarchy? I didn't find an option in the documentation of vcom. Only link I found is this, where the…
Marph
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