In system verilog, I know you can route a partial bus with array[15:8] as a way to split lanes. Is there any way to do this in a non continuous way. For example, lane 2,3,8,9 .
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You can connect the in any way:
For example:
assign a[0] = b[2];
assign a[1] = b[3];
assign a[3:2] = b[9:8];

Enze Chi
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Thankyou, I thought that was for array defining, not bus routing. – Ryu Apr 24 '18 at 17:37
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Alternative to Enze Chi way is to use concatenation:
wire [3:0] a;
assign a = {b[9:8],b[3],b[2]};

Oldfart
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The {...} operator just 'glues' bits or vectors together. Beware of the size of the values inside the brackets. e.g. a constant '3' will add 32 bits! – Oldfart Apr 24 '18 at 18:05