Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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1 answer

Booth encode not working, simulation included

I am writing a Booth encode for array multiplier. This is one of the module: module add_input (M,pos,neg,C); parameter n=8; input [n-1:0]M; input pos,neg; output [2*n-1:0]C; reg [2*n-1:0]C; integer k; always @ (*) begin for…

verilog system-verilog modelsim

asked Feb 17 '12 at 04:42

fiftyplus

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0 answers

synopsys tetramax strange error in parcing vectors from VCD

I am a Tetramax Newby and i am trying to get a mesure of fault coverage loading functional test vector generated by modelsim. I generate the modelsim test vector following this procedure: vsim work.TbTop view wave wave create -pattern none -portmode…

dump vhdl modelsim

asked Nov 30 '11 at 10:39

Stefano

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How to do the same thing as the "compile all" button in Modelsim

In Modelsim there is a "compile all" button that compiles all the files in the project so that they can be simulated. But when the button is pressed it doesn't show what those commands are? What are the commands to enter in the terminal to do the…

modelsim

asked Nov 26 '11 at 08:44

node ninja

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How can I stop the simulation at stop bit for I2C master code?

I am trying to write Verilog code for I2C master, and there are a couple of problems I am facing. I was able to compile and run its testbench on Quartus and modelsim, respectively. However, I am trying to have it switch back to reset mode on (reset…

verilog i2c modelsim quartus

asked Jun 05 '23 at 22:09

Qazi Zabeer

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2 answers

Strange error in ModelSim but not in Quartus?

I'm doing a Verilog project on quartus, and when I do the analysis and synthesis, quartus doesn't give me any errors. When instead I try to compile the files on ModelSim, it gives me the following error: ** Error:…

verilog modelsim

asked May 15 '23 at 16:41

Dev

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1 answer

Error with Multiply-Accumulation Verilog Simulation: Illegal output or inout port connection

I'm trying to build a Multiply-Accumulator (MAC) module for Matrix Multiplier with Verilog. Here's Verilog Code for the MAC module: module Multiply_Accumulation(MAC_out, sel, a, b, clk, rstn); //multiply 8bit a, b and accumulate through Adder …

verilog simulation multiplication modelsim

asked May 04 '23 at 05:20

DJJJ

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2 answers

Why does this Verilog module output x even though it has non-X inputs?

I am trying to create a 4-bit ripple carry adder using 4 full adders each comprised of two half-adders. This is the code for my half-adder: module HA (input a, b, output reg cout, output reg sum); reg [1:0] temp; always @ (a or b)…

verilog hdl modelsim

asked Apr 21 '23 at 14:15

Amir Kooshky

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2 answers

How to access signals in submodules with multiple modules?

I have the following Verilog file named main.v: module m1(input a, b, output wire c); assign c = a & b; endmodule module main(input x, y, output wire z); wire k; m1 m1_inst(.a(x), .b(y), .c(k)); assign z = x ^ k; endmodule After that, I have a…

verilog system-verilog modelsim test-bench

asked Feb 26 '23 at 16:04

Ahsan Ali

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1 answer

Why do I get a syntax error for omitting a semicolon after one #10, but it is not needed for others?

My friend wrote an FSM code that generates 3 numbers (1,4,1) in binary. The code works and compiles in modelsim. I wrote a testbench for it so I can simulate it. The testbench code errors in line 24 and says this: ** Error: (vlog-13069)…

verilog system-verilog modelsim test-bench

asked Jan 18 '23 at 15:39

rady alz

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2 answers

Random number generator using $dist_uniform in SystemVerilog

I am trying to generate a random number using the $dist_uniform using Quartus and ModelSim. The relevant code section is as follows (within a loop): rand= $dist_uniform(10,20,25); rand_test=$random; 'rand' is always 20 while 'rand_test' is varied…

random verilog distribution system-verilog modelsim

asked Jan 16 '23 at 14:39

shlopkin

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1 answer

why output of 2nd function call to 4 bit adder is X(don't care)?

I am new to verilog, I was building a 32-bit adder using structural modelling. So I made a 1-bit full adder, then used that to construct a 4-bit adder, and that was used to create an 8- bit adder. Everything works fine until the 4-bit adder but when…

verilog modelsim

asked Oct 29 '22 at 23:33

Sachin Mirajkar

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1 answer

Trying to simulate a BCD adder: unexpected IDENTIFIER error

I'm trying to simulate a BCD adder by instantiating full adder modules. Compiling the code without the test module ran fine. However, I'm currently having issues with my testbench. It's showing an error: near "tb_C": syntax error, unexpected…

verilog system-verilog modelsim test-bench

asked Sep 29 '22 at 09:28

user15134999

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1 answer

Transposed form fir filter in vhdl

I am trying to implement a transposed form FIR filter of order 4.I am attaching the code and the waveform alongwith.In the first clock cycle, I have given a reset signal which will initialize the adder_output to 0.Input data is loaded in the second…

filter vhdl simulation modelsim

asked Jul 15 '22 at 05:48

Deepa

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1 answer

IEEE 754-2008 Float32 calculations incorrect in HDL simulators

If I try to use calculations with infinity results (in float32 representation) there are some unexpected results, as if the calculations were in double precision. Simple casts to shortreal doesn't work, only conversion to bits and back again. module…

verilog fpga ieee-754 modelsim infinity

asked Jul 13 '22 at 21:18

Mogwaika

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1 answer

Is there any other way to initialize a module in Verilog?

I am new to verilog. In my predefined processor design, control module is defined as: module control(in,regdest,alusrc,memtoreg,regwrite,memread,memwrite,branch,funct,branch_cont0,branch_cont1,branch_cont2,aluop0,aluop1,aluop2); but later in the…

module initialization verilog modelsim

asked May 29 '22 at 22:55

Mahmut Salman

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