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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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I wrote this code in Verilog and there are no error messages, but it doesn't work

This is the module: module test (output reg [7:0] Q_out, input [2:0] data_in); always begin case (data_in) 3'b000: Q_out = 8'b10000000; 3'b001: Q_out = 8'b01000000; 3'b010: Q_out = 8'b00100000; 3'b011:…
gela gela
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I think it is a bug. ModelSim cannot be called from Quartus on Ubuntu

I have Quartus Prime Lite 21.1 installed on Ubuntu 20.04 and it is working fine. I also have ModelSim 20.1.1 and it is working fine I've put the right path to ModelSim on Quartus Prime, and it can even recognize the version (unfortunantly, I'm…
domvito55
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Why this process is executed when the simulation starts

This is a simple entity just to know the usage of "process" My question is: Why the process is executed when the simulation just starts? I think the process wakes up when the signals in the sensitivity list change, but in this example, the…
Hao Alessandro
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Modelsim shows an unknown warning about vmap command

I created the library "work", but then when I try to use the command "vmap work work" I get the following warning about 20 times in a row: " ** Warning: (vmap-7) Failed to open lock file…
Serad01
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Unexpected warning in Verilog simulation for port size

I couldn't figure out why the simulator gives the warning and why the circuit does not work properly. This is the Verilog code: `timescale 1ns/1ns module circuitIVEightBitAssign(input [7:0]a,flag,output [7:0]b); assign #(143) b = flag ? ~a :…
Ali Eftekhari
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Expecting a vector value and getting an array instead for a reg

I am trying to create Verilog code which allows for an LED to blink at a certain frequency. I have a reg that I am using as a counter that I think should be a vector but is instead saying it's a packed array in ModelSim. VERILOG CODE module main( …
JTH828
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Passing $args as a substitution for vsim arguments gives an error

I want to use $args as a substitution for some of the vsim arguments. ** UI-Msg: (vish-3296) Unknown option '-assertdebug -classdebug' vlog -sv time_diff_test.sv vopt time_diff_test +acc -o dbgver set args "-assertdebug -classdebug" vsim dbgver…
eminakgn
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Setting signals length using received parameters in SystemC

context I'm making a simulation environment with systemC co-simulated with verilog/VHDL RTL modules using modelsim/questasim My Verilog modules use parameters to set up each module My VHDL modules use generics to set up each module My systemC…
NicolasDg
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test bench is no working. z and x states in modelsim

i realized a bubble sort code on verilog. there are no any synthesis erorrs, but test bench is not working in modelsim. it shows x and z states module sort #( parameter NUM_VALS = 5, parameter SIZE = 16 )( input wire clk, input …
dduy_le
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Override default_nettype in ModelSim

I would like to change default_nettype in my RTL design without explicitly modifying the respective compiler directive within each file. Is there a way to override it in ModelSim software?
yildizabdullah
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How to define parameters in a generate block and access them outside?

I want to define some local parameters whose values are decided by a parameter assigned outside this module. Here, I use a generate block. Just like the following: module doppler_fft_cluster # ( parameter CORE_TYPE = "DOPPLER_FFT_D0" ) ( clk,…
Bob Green
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Is it possible to call do files from a tcl script in modelsim?

I tried to write an automatic script for modelsim, where I would go through each possible malfunction in the circuit one by one, and then analyze it. For one malfunction, I did everything, and it works, however when I tried to make a loop where I…
artkuv
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how to use the force command with a type unsigned(n downto 0) in modelsim when simulating a VHDL file?

When initializing inputs for a test, as I understand, you have to use the force command. For example to create a clock cycle, counting that the entity I'm simulating has an input named clock, which is of type std_logic, I would usually write force…
motelepf
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Cannot create a project in modelsim

I've downloaded Modelsim from this website (https://fpgasoftware.intel.com/?product=modelsim_ae#tabs-2) to be specific I downloaded the ModelSim-Intel FPGA Started Edition Part 1 and 2.AFter installing I went to create a project and this is the…
codeisfun
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Port size (12 or 12) does not match connection size (6)

Booth algorithm is a multiplication operation that multiplies two numbers in two complement notation The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing the number of partial…
Programming Learner
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