How to access signals in submodules with multiple modules?

Question

I have the following Verilog file named main.v:

module m1(input a, b, output wire c);

assign c = a & b;

endmodule

module main(input x, y, output wire z);

wire k;
m1 m1_inst(.a(x), .b(y), .c(k));
assign z = x ^ k;

endmodule

After that, I have a test bench named tb_main.v which has an instantiation as shown below:

`include "main.v"
reg a, b;
wire b;
main main_dut(a, b, c);

$display("%b", main_dut.m1.a);
$display("%b", main_dut.main.y);
$display("%b", m1.a);

When I simulate that testbench, I get the error unresolved reference to m1 and unresolved reference to main.

How do I solve this problem? I do not want to separate modules in the main.v file into different files. Any help will be appreciated.

Answer 1

The problem is that you are using some module names instead of module instance names in your hierarchical specifiers.

For example, in main_dut.m1.a:

• main_dut is a module instance name
• m1 is the name of the module, not the instance

You must only use module instance names. This is a complete code example that compiles without errors (also on EDA Playground):

module m1 (input a, b, output wire c);
    assign c = a & b;
endmodule

module main (input x, y, output wire z);
    wire k;
    m1 m1_inst (.a(x), .b(y), .c(k));
    assign z = x ^ k;
endmodule

module tb_main;
    reg a, b;
    main main_dut (a, b, c);
    initial $display("%b", main_dut.m1_inst.a);
    initial $display("%b", main_dut.y);
endmodule

Answer 2

It is always better to maintain explicit connectivity. So instead of

reg a, b;
wire b;
main main_dut(a, b, c);

, do something like

reg a, b;
wire b;
main main_dut(
               .a(a),
               .b(b),
               .c(c)
             );