Trying to simulate a BCD adder: unexpected IDENTIFIER error

Question

I'm trying to simulate a BCD adder by instantiating full adder modules. Compiling the code without the test module ran fine. However, I'm currently having issues with my testbench. It's showing an error:

near "tb_C": syntax error, unexpected IDENTIFIER, expecting .* or '.'.

I'm currently trying to learn the top-down approach of HDL.

//Half Adder (HA) module
module half_adder(output S, Co, input a, b);

    xor U1(S, a, b); 
    and U2(Co, a, b);
    
endmodule

//Full Adder (FA) module
module full_adder(output S, Co, input a, b, cin); 

    wire ha_S0, ha_Co0, ha_Co1; 

    half_adder HA1(ha_S0, ha_Co0, a, b);   //instance 1 of HA
    half_adder HA2(S, ha_Co1, ha_S0, cin); //instance 2 of HA

    or U3(Co, ha_Co0, ha_Co1); 
    
endmodule

//4-bit Full Parallel Adder
module yonbit_pa(input [3:0]a, [3:0]b, cin, output [3:0]S, Cout);

    wire [2:0]Co;

    full_adder FA1(S[0], Co[0], a[0], b[0], cin);
    full_adder FA2(S[1], Co[1], a[1], b[1], Co[0]);
    full_adder FA3(S[2], Co[2], a[2], b[2], Co[1]);
    full_adder FA4(S[3], Cout,  a[3], b[3], Co[2]);

endmodule

//Single Digit BCD Adder

module bcd_adder(input [3:0]a, [3:0]b, cin, output C, [3:0]D);

    supply0 gnd;
    wire Co;
    wire [3:0]S;
    wire [2:0]orin;

    fourbit_pa PA1(S[0], S[1], S[2], S[3], Co, a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], cin);
    
    and U4(orin[0], S[3], S[2]), U5(orin[1], S[3], S[1]);
    or  U6(orin[2], orin[1], orin[0]), U7(C, orin[2], Co);

    fourbit_pa PA2(D[0], D[1], D[2], D[3], S[0], S[1], S[2], S[3], gnd, C, C, gnd, gnd);

endmodule

//Testbench
module mut_bcd_adder;

    reg [3:0]a;
    reg [3:0]b;
    reg cin;
    wire C;
    wire [3:0]D;

    bcd_adder mut_bcd_adder(.a(tb_a),.b(tb_b),.cin(tb_cin), tb_C, tb_D);
    
    initial begin
        
        $display("                 Time a     b    cin    C D");
        $monitor($time,,"%b %b  %b  %b  %b", tb_a, tb_b, tb_cin, tb_C, tb_D);

        #0 tb_cin = 1'b0; tb_a = 4'b0000; tb_b = 4'b0000;
        #5 tb_cin = 1'b0; tb_a = 4'b0011; tb_b = 4'b1001;
        #5 tb_cin = 1'b0; tb_a = 4'b1000; tb_b = 4'b0111;
        #5 tb_cin = 1'b0; tb_a = 4'b0100; tb_b = 4'b0100;
        #5 tb_cin = 1'b0; tb_a = 4'b0111; tb_b = 4'b0010;
        #5 tb_cin = 1'b1; tb_a = 4'b1001; tb_b = 4'b0110;
        #5 tb_cin = 1'b1; tb_a = 4'b0011; tb_b = 4'b0011;
        #5 tb_cin = 1'b1; tb_a = 4'b0111; tb_b = 4'b0111;
        #5 tb_cin = 1'b1; tb_a = 4'b0010; tb_b = 4'b0110;
        #5 $finish;
    
    end
endmodule

score 0 · Answer 1 · answered Sep 29 '22 at 09:46

If you run your code on different simulators on EDA Playground, you will get slightly more helpful compile error messages. Taken together, you get a clearer picture of the problem. For example, with VCS:

Error-[MPC] Mixed port connection is not allowed
testbench.sv, 
  The two types of module port connections, by ordered list and by name, shall
  not be mixed.
  Please refer to Verilog LRM(1364-2001), section 12.3.6.

1 error

Change:

bcd_adder mut_bcd_adder(.a(tb_a),.b(tb_b),.cin(tb_cin), tb_C, tb_D);

to:

bcd_adder mut_bcd_adder(.a(tb_a),.b(tb_b),.cin(tb_cin), .C(tb_C), .D(tb_D));

The point is that you need to use the same port connection style for all the ports.

You have other syntax errors that you need to fix. You need to declare all the signals in the testbench: tb_a, tb_b, etc.

Trying to simulate a BCD adder: unexpected IDENTIFIER error

1 Answers1