synopsys tetramax strange error in parcing vectors from VCD

Question

I am a Tetramax Newby and i am trying to get a mesure of fault coverage loading functional test vector generated by modelsim. I generate the modelsim test vector following this procedure:

vsim work.TbTop
view wave
wave create -pattern none -portmode out -language vhdl -range 15 0 //tbtop/outport
restart TbTop.vhd
vcd dumpports -file alwcpuSimDump.vcd /TbTop/alwcpu66/*
run 1000
quit -sim

and i later load such a VCD in tetramax with the following command

set patterns external ./externalFaults/alwcpuSimDump.vcd -insensitive -strobe rising clock -strobe offset 180 ns

First error appearing was the fact that signals where capital and lower case in different files (solved by using -insensitive). Second problem is that std_logic_vector are not recognised while parcing the VCD.

This is the error I get:

missing definition (No such port "adr_o[15]"). (V4-1)

but in the VCD the port is present as shown here:

$var port 1 <0 clk_i $end
$var port 1 <1 rst_i $end
$var port 1 <2 cyc_o $end
$var port 1 <3 stb_o $end
$var port 1 <4 sel_o $end
$var port 1 <5 we_o $end
$var port 1 <6 ack_i $end
$var port [15:0] <7 adr_o $end
$var port [15:0] <8 dat_o $end
$var port [15:0] <9 dat_i $end

as well as it is present in the netlist as shown here:

entity cpu is
   port( CLK_I, RST_I : in std_logic;  CYC_O, STB_O, SEL_O, WE_O : out 
         std_logic;  ACK_I : in std_logic;  ADR_O, DAT_O : out std_logic_vector
         (15 downto 0);  DAT_I : in std_logic_vector (15 downto 0));
end cpu;

did anyone experienced such a problem? Any idea about why this happens or how to fix it??

Cheers,

synopsys tetramax strange error in parcing vectors from VCD

0 Answers0