I am trying to generate a random number using the $dist_uniform using Quartus and ModelSim.
The relevant code section is as follows (within a loop):
rand= $dist_uniform(10,20,25);
rand_test=$random;
'rand' is always 20 while 'rand_test' is varied on every iteration.
Would appreciate any advice on the matter.
I have tried many variations of the $dist_uniform as well as other distributions as well - the only way I have succeeded to generate a random number is by the $random command.
The first argument to the $dist_uniform function should be an integer variable, not a constant. Refer to IEEE Std 1800-2017, section 20.15.2 Distribution functions.
$dist_uniform ( seed , start , end )
... the seed argument is an inout argument; that is, a value is passed to the function, and a different value is returned.
This produces 10 random integers between 20 and 25:
module tb;
integer rand_test, seed;
initial begin
repeat (10) begin
rand_test = $dist_uniform(seed, 20, 25);
$display(rand_test);
end
end
endmodule
Also, rand is a SystemVerilog (IEEE Std 1800) keyword. Trying to assign to it should give you a compile error. Many simulators require you to explicitly enable SV features.
Your use of $dist_random has a constant seed, so it always returns the same random value. In SystemVerilog, you should be using $urandom_range(maximal, minval=0) instead of $dist_uniform(seed, start, end), as well as $urandom instead of $random Even if your design is in Verilog, these system function should still be available for use in your testbench.
The $urandom function in SystemVerilog have much better uniform distributions of values and offer much better random stability (the ability to reproduce the same series of random values for debugging stimulus).
