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I'm encountering an error with running my testbench as whenever I input try to run it with the vvp command, I only get a message that reads "SantiJ1.v:1:syntax error". I've looked through my code and there doesn't seem to be a problem, at least from what I can see.

Here's the module:

`timescale 1ns/1ps

module HDLProject1(A, B, C, D, AB, BA, P1, P2, F);

    input A, B, C, D;
    output nA, nB, nD, AB, BA, P1, P2, F;

    not notA(nA, A);
    not notB(nB, B);
    and Part1(AB, A, nB);
    and Part2(BA, B, nA);
    or  Level1(P1, AB, BA);
    not notD(nD, D);
    or  Level2(P2, C, nD);
    and Finish(F, P1, P2);

endmodule

And here's the testbench:

`timescale 1ns/1ps

module HDLProject_tb;

    reg test_A, test_B, test_C, test_D;
    wire test_AB, test_BA, test_P1, test_P2, test_F;

    HDLProject1 dut(test_A, test_B, test_C, test_D, test_AB, test_BA, test_P1, test_P2, test_F);
    initial
        begin
            test_A = 0;
            test_B = 0;
            test_C = 0;
            test_D = 0; 

            #10 
            test_A = 0;
            test_B = 0;
            test_C = 0;
            test_D = 1; 

            #10 
            test_A = 0;
            test_B = 0;
            test_C = 1;
            test_D = 0;

            #10 
            test_A = 0;
            test_B = 0;
            test_C = 1;
            test_D = 1; 

            #10 test_A = 0;
            test_B = 1;
            test_C = 0;
            test_D = 0; 

            #10 
            test_A = 0;
            test_B = 1;
            test_C = 0;
            test_D = 1; 

            #10 test_A = 0;
            test_B = 1;
            test_C = 1;
            test_D = 0;

            #10 
            test_A = 0;
            test_B = 1;
            test_C = 1;
            test_D = 1;  

            #10 test_A = 1;
            test_B = 0;
            test_C = 0;
            test_D = 0; 

            #10 
            test_A = 1;
            test_B = 0;
            test_C = 0;
            test_D = 1; 

            #10 
            test_A = 1;
            test_B = 0;
            test_C = 1;
            test_D = 0; 

            #10 
            test_A = 1;
            test_B = 0;
            test_C = 1;
            test_D = 1; 

            #10 
            test_A = 1;
            test_B = 1;
            test_C = 0;
            test_D = 0; 

            #10 
            test_A = 1;
            test_B = 1;
            test_C = 0;
            test_D = 1; 

            #10 
            test_A = 1;
            test_B = 1;
            test_C = 1;
            test_D = 0; 

            #10 
            test_A = 1;
            test_B = 1;
            test_C = 1;
            test_D = 1; 
         end
        
    initial
        begin
        $monitor("time = %0d", $time, " A = %b  B = %b  C = %b  D = %b Output_F = %b", test_A, test_B, test_C, test_D, test_F);
        $dumpfile("SantiJ1.vcd");
        $dumpvars();
        end
endmodule

From what I can gather from the error message, it only points to line 1, but I can't really point a finger at a possible cause for the error as I'm new to using HDLs.

Ram Santiago
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    which one is in the file 'SantiJ1.v'? How is yor vpp command looks like? From these two pieces the only error is that you list nA, nB, and nD as output, while they are not in the port list of the module. – Serge Jul 31 '21 at 01:06
  • The file with that name is for the first piece, but the error appears when I use the vvp on the module or the testbench. – Ram Santiago Jul 31 '21 at 01:40
  • There are no syntactic errors in the code. Either you have an issue with your vvp command or you are missing some pieces. Check if there are any unprintable symbols in your file or if you use a utf encoding. I tried it in eda playground with a few compilers. No syntactic issues. – Serge Jul 31 '21 at 02:08

1 Answers1

-1

Are you observing the following error?

$ vvp SantiJ1.v HDLProject_tb.v 
SantiJ1.v:1: syntax error

The issue is that that vvp isn't supposed to be used that way. What you need to do is:

$ iverilog HDLProject_tb.v SantiJ1.v
$ vvp ./a.out 
VCD info: dumpfile SantiJ1.vcd opened for output.
time = 0 A = 0  B = 0  C = 0  D = 0 Output_F = 0
time = 10 A = 0  B = 0  C = 0  D = 1 Output_F = 0
time = 20 A = 0  B = 0  C = 1  D = 0 Output_F = 0
time = 30 A = 0  B = 0  C = 1  D = 1 Output_F = 0
time = 40 A = 0  B = 1  C = 0  D = 0 Output_F = 1
time = 50 A = 0  B = 1  C = 0  D = 1 Output_F = 0
time = 60 A = 0  B = 1  C = 1  D = 0 Output_F = 1
time = 70 A = 0  B = 1  C = 1  D = 1 Output_F = 1
time = 80 A = 1  B = 0  C = 0  D = 0 Output_F = 1
time = 90 A = 1  B = 0  C = 0  D = 1 Output_F = 0
time = 100 A = 1  B = 0  C = 1  D = 0 Output_F = 1
time = 110 A = 1  B = 0  C = 1  D = 1 Output_F = 1
time = 120 A = 1  B = 1  C = 0  D = 0 Output_F = 0
time = 130 A = 1  B = 1  C = 0  D = 1 Output_F = 0
time = 140 A = 1  B = 1  C = 1  D = 0 Output_F = 0
time = 150 A = 1  B = 1  C = 1  D = 1 Output_F = 0

In point of fact, ./a.out's first line includes the necessary shell magic to be runnable by default. So, you can run it directly:

$ head -1 ./a.out 
#! /usr/bin/vvp
$ ./a.out
Tinkerer
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