0

I have a big issue with an 8-bit ALU. To begin with, the code won't stop running. Second, a chart of specifications was given, and I believe I'm missing some of them

Here are the specifications:

Specification
Data Inputs: A (8-bit), B (8-bit)
Control Inputs: S (1-bit), E (1-bit)
Output: W (8-bit)

The output W should be 0 if E = 0. If E = 1, then W = A + B for S = 0, and W = A - B for S = 1.

Here is the code:

`timescale 1ns / 1ps

module ALU8bit( Opcode,

                Operand1,

                Operand2,

                Result,

                flagC,

                flagZ

              );    

input [2:0]  Opcode;

input [7:0]  Operand1,

             Operand2;

     

output reg [15:0] Result = 16'b0;

output reg  flagC = 1'b0,

            flagZ = 1'b0;   

parameter  [2:0] ADD = 3'b000,

                 SUB = 3'b001,

                 MUL = 3'b010,

                 AND = 3'b011,

                 OR = 3'b100,

                 NAND = 3'b101,

                 NOR = 3'b110,

                 XOR = 3'b111;      

always @ (Opcode or Operand1 or Operand2)

begin

 case (Opcode)

 ADD: begin

   Result = Operand1 + Operand2;

   flagC  = Result[8];

   flagZ  = (Result == 16'b0);

  end

 SUB: begin

   Result = Operand1 - Operand2;

   flagC  = Result[8];

   flagZ  = (Result == 16'b0);

  end

 MUL: begin

   Result = Operand1 * Operand2;

   flagZ  = (Result == 16'b0);

  end

 AND: begin

   Result = Operand1 & Operand2;

   flagZ  = (Result == 16'b0);

  end

 OR:  begin

    Result = Operand1 | Operand2;

    flagZ  = (Result == 16'b0);

   end

 NAND: begin

   Result = ~(Operand1 & Operand2);

   flagZ  = (Result == 16'b0);

  end

 NOR: begin

   Result = ~(Operand1 | Operand2);

   flagZ  = (Result == 16'b0);

  end

 XOR: begin

   Result = Operand1 ^ Operand2;

   flagZ  = (Result == 16'b0);

  end

 default: begin

   Result = 16'b0;

   flagC  = 1'b0;

   flagZ  = 1'b0;

  end

 endcase

end

endmodule

and here is the testbench:

`timescale 1ns / 1ps
`include "alu_8bit.v"
module alu_8bit_test;

 // Inputs

 reg [2:0] Opcode;

 reg [7:0] Operand1;

 reg [7:0] Operand2;

 // Outputs

 wire [15:0] Result;

 wire flagC;

 wire flagZ;

 //Temporary variable

 reg [2:0] count = 3'd0;

 // Instantiate the Unit Under Test (UUT)

 ALU8bit uut (

  .Opcode(Opcode), 

  .Operand1(Operand1), 

  .Operand2(Operand2), 

  .Result(Result), 

  .flagC(flagC), 

  .flagZ(flagZ)

  );

 initial begin
     $display("Start of Test.");
        $dumpfile("alu_8bit.vcd");
        $dumpvars(0, alu_8bit_test);
        // Initialize Inputs

        Opcode   = 3'b0;

        Operand1 = 8'd0;

         Operand2 = 8'd0;

         // Wait 100 ns for global reset to finish

         #100;    
           $display("End of Test.");
        // Add stimulus here  

         Operand1 = 8'hAA;

         Operand2 = 8'h55;  

         for (count = 0; count < 8; count = count + 1'b1) 

         begin

            Opcode = count;

            #20;
        end

    end     

endmodule

I really appreciate any help you guys can provide me with.

toolic
  • 57,801
  • 17
  • 75
  • 117
GHG HGH
  • 37
  • 3

1 Answers1

0

The range of your count variable is 0 to 7. This means count will always be less than 8, and your count < 8 expression will always be true. This causes the for loop to be an infinite loop, which is why the simulation never stops.

Change:

reg [2:0] count = 3'd0;

to:

integer count = 0;
toolic
  • 57,801
  • 17
  • 75
  • 117