Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

Official site: http://iverilog.icarus.com
Source code: https://github.com/steveicarus/iverilog
Wikipedia

176 questions

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2 answers

GtkWave isn't getting signals from IVerilog simulation

I wrote the following test for my code: module HalfAdder_Test; wire sum; wire carry; reg a = 0; reg b = 0; initial begin $dumpfile("test.vcd"); $dumpvars(0, HalfAdder_Test); # 10 a = 0; # 10 b = 0; # 30 a = 1; # 30 b =…

verilog iverilog gtkwave

asked Jul 01 '17 at 18:58

Tyler Hilbert

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Icarus doesnt know how to parse localparam arrays?

I am using v10 of Icarus Verilog, Windows 8.1 and am having troubles compiling 1D arrays like: localparam [15:0] A[0:5] = { 0, 10920, 21840, 32760, 43680, 54600 }; or 2D array like: localparam [1:0] B[0:5][0:2] = { …

arrays verilog iverilog

asked Jun 02 '17 at 09:31

user1806687

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1 answer

Output of "for" is unknown instead of 1 in Verilog

I'm using Icarus iVerilog to synthesize and test my code but I'm getting unknown values when logically 1's should be appearing. Here's an example of what I'm trying to do. reg [8:0] a = 000110100; wire [8:0] b = 0; generate genvar i; for (i…

for-loop verilog iverilog

asked Jul 31 '16 at 20:54

adragon202

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2 answers

How do I access an array element using a variable as index?

I'm trying to access an element from an array using an input as index and I keep getting this error: cache.v:27: error: array 'tagc' index must be a constant in this context. Here's how I'm trying to do it: assign tagc[index] = tag; tagc is an…

arrays reference verilog iverilog

asked Jun 30 '16 at 22:25

Ariel Jorge Rossi

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1 answer

How to call tasks from a separate module in Verilog?

I'm new to Verilog and would really appreciate it if someone could help me with this. I have a task written in a separate file - "task.v" : module task_create(); task assign_inp; reg a,b,c,d; //details endtask endmodule I have a module…

task verilog iverilog

asked Jun 03 '16 at 23:43

AnnaR

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1 answer

Declaration of a Verilog function in a header file

When I try to compile a testbench which includes a header file which contains a function declaration Icarus Verilog (v10.0 stable) aborts with the following error: mpeg.vh:133: error: function declarations must be contained within a module. This…

verilog system-verilog xilinx iverilog

asked Feb 20 '16 at 11:13

andrsmllr

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1 answer

Implementing one-bit flags in a 32Bit ALU using Verilog

I am working on an assignment and am a little lost and don't really know how to get started. I need to implement the following flags in a 32Bit ALU: • Z ("Zero"): Set to 1 ("True") if the result of the operation is zero • N ("Negative"): Set to 1…

verilog digital-logic alu iverilog status-register

asked Dec 06 '15 at 00:35

Scruffy Nerfherder

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1 answer

4Way Demultiplexer circuit using Verilog

I am struggling here on an assignment for my digital logic class. I have searched online for resources, but there is not much that has proven to be helpful. It seems that everyone has a different approach than what we are doing in class. There is no…

verilog digital-logic iverilog

asked Nov 29 '15 at 21:02

Scruffy Nerfherder

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1 answer

Gate Cost of 16 bit Ripple carry adder, and 16 bit (Two Level) Carry Look Ahead Adder

Hi i was just curious what would be the gate cost of combinational 16 bit Ripple carry adder, and 16 bit (Two Level) Carry Look Ahead Adder. Thanks

verilog system-verilog circuit circuit-diagram iverilog

asked Nov 24 '15 at 00:09

jake

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0 answers

Verilog Memory Component Input

I'm working on a lab in Verilog and one of the tasks tells me to write different contents to 2 different addresses. Here is my code: module labM; reg [31:0] address, memIn; reg clk, read, write; integer i; wire [31:0] memOut; mem data(memOut,…

verilog iverilog

asked Nov 15 '15 at 02:08

M. Averbach

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0 answers

No top level modules, and no -s option error in my VScode

I'm getting an error on icarus iverilog code in vscode this is my hello.v file content module hello(a,b); input a; output b; assign b = a; endmodule this is my hello_tb.v file content `timescale 1ns/1ps `include "hello.v" module…

visual-studio-code verilog iverilog

asked Sep 01 '23 at 05:23

Prathik N.K

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1 answer

$dumpfile and $dumpvars not working in vscode error in terminal says requires system verilog

Elaboration task '$dumpvars' requires SystemVerilog is the error that is showing in the terminal when I execute iverilog -o test_tb.vvp test_tb.v similar for $dumpvars the codes are //design module test (a,b); input a; output b; …

verilog system-verilog iverilog icarus

asked Apr 01 '23 at 12:55

Chomusuke

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1 answer

No such file or directory No top level modules, and no -s option

I have Icarus Verilog installed on macos, but when I run it in the terminal to get a .vcd file, it always give me these messages: ben@Bens-macbook ~ % iverilog -o khanh.vvp khanh_tb.v khanh_tb.v: No such file or directory No top level modules, and…

macos verilog iverilog

asked Feb 08 '23 at 17:28

KHÁNH PHẠM NGUYỄN HẢI

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2 answers

In Verilog how "wire" data type is managed in computer memory?

It's easy to visualize how computer manages to store reg & int variables in memory. Just allocating 1/32 bits respectively in memory and storing the initializing value in binary form. When these variables need to be printed, they are converted back…

hdl iverilog

asked Jan 02 '23 at 11:26

Ayush Gemini

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1 answer

Initialize parameter from array

I have a parameterised module whose SEED value has to change depending on the WIDTH parameter, where the seed values have to be hard-coded. module Module; parameter WIDTH = 8; integer seeds [31:0] = {'hC, 'h1E, 'h39, 'h7E, /* ... */}; localparam…

verilog iverilog

asked Nov 04 '22 at 13:16

Inigo Selwood

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