Why do I get Syntax Error in Assignment statement l-value?

Question

I cannot find the syntax error in this code of a MIPS decoder. I am currently inside of the default case, and it gives me the errors

Decoder.v:104: syntax error.

Decoder.v:106: Syntax in assignment statement l-value

Here is the code:

module Decoder(
    input     [31:0] instr,      // Instruktionswort
    input            zero,       // Liefert aktuelle Operation im Datenpfad 0 als Ergebnis?
    output reg       memtoreg,   // Verwende ein geladenes Wort anstatt des ALU-Ergebis als Resultat
    output reg       memwrite,   // Schreibe in den Datenspeicher
    output reg       dobranch,   // Führe einen relativen Sprung aus
    output reg       alusrcbimm, // Verwende den immediate-Wert als zweiten Operanden
    output reg [4:0] destreg,    // Nummer des (möglicherweise) zu schreibenden Zielregisters
    output reg       regwrite,   // Schreibe ein Zielregister
    output reg       dojump,     // Führe einen absoluten Sprung aus
    output reg [2:0] alucontrol  // ALU-Kontroll-Bits
);
    // Extrahiere primären und sekundären Operationcode
    wire [5:0] op = instr[31:26];
    wire [5:0] funct = instr[5:0];

    always @*
    begin
        case (op)
            6'b000000: // Rtype Instruktion
                begin
                    regwrite = 1;
                    destreg = instr[15:11];
                    alusrcbimm = 0;
                    dobranch = 0;
                    memwrite = 0;
                    memtoreg = 0;
                    dojump = 0;
                    case (funct)
                        6'b100001: alucontrol = 101; // TODO // Addition unsigned
                        6'b100011: alucontrol = 001; // TODO // Subtraktion unsigned
                        6'b100100: alucontrol = 111; // TODO // and
                        6'b100101: alucontrol = 110; // TODO // or
                        6'b101011: alucontrol = 000; // TODO // set-less-than unsigned
                        default:   alucontrol = 011; // TODO // undefiniert
                    endcase
                end
            6'b100011, // Lade Datenwort aus Speicher
            6'b101011: // Speichere Datenwort
                begin
                    regwrite = ~op[3];
                    destreg = instr[20:16];
                    alusrcbimm = 1;
                    dobranch = 0;
                    memwrite = op[3];
                    memtoreg = 1;
                    dojump = 0;
                    alucontrol = 011; // TODO // Addition effektive Adresse: Basisregister + Offset
                end
            6'b000100: // Branch Equal
                begin
                    regwrite = 0;
                    destreg = 5'bx;
                    alusrcbimm = 0;
                    dobranch = zero; // Gleichheitstest
                    memwrite = 0;
                    memtoreg = 0;
                    dojump = 0;
                    alucontrol = 001; // TODO // Subtraktion
                end
            6'b001001: // Addition immediate unsigned
                begin
                    regwrite = 1;
                    destreg = instr[20:16];
                    alusrcbimm = 1;
                    dobranch = 0;
                    memwrite = 0;
                    memtoreg = 0;
                    dojump = 0;
                    alucontrol = 101; // TODO // Addition
                end
            6'b000010: // Jump immediate
                begin
                    regwrite = 0;
                    destreg = 5'bx;
                    alusrcbimm = 0;
                    dobranch = 0;
                    memwrite = 0;
                    memtoreg = 0;
                    dojump = 1;
                    alucontrol = 011; // TODO
                end
            6'b001111: //Load upper immediate
                begin
                    regwrite = 1;
                    destres = intsr[20:16];
                    alusrcbimm = 1;
                    dobranch = 0;
                    memwrite = 1;
                    memtoreg = 0;
                    dojump = 0;
                    alucontrol = 011; // Bitshift.
                end
            6'b001101: //Bitwise or immediate
                begin
                    regwrite = 1;
                    destreg = instr[20:16];
                    alusrcbimm = 1;
                    dobranch = 0;
                    memwrite = 0;
                    memtoreg = 0;
                    dojump = 0;
                    alucontrol = 110; //Bitwise or.
            default: // Default Fall
                begin
                    regwrite = 1'bx;
                    destreg = 5'bx;
                    alusrcbimm = 1'bx;
                    dobranch = 1'bx;
                    memwrite = 1'bx;
                    memtoreg = 1'bx;
                    dojump = 1'bx;
                    alucontrol = 011; // TODO
                end
        endcase
    end
endmodule

score 1 · Accepted Answer · answered Jul 01 '20 at 16:53

I get 2 compile errors.

The 1st is due to a missing end statement before the default:

        6'b001101: //Bitwise or immediate
            begin
                regwrite = 1;
                destreg = instr[20:16];
                alusrcbimm = 1;
                dobranch = 0;
                memwrite = 0;
                memtoreg = 0;
                dojump = 0;
                alucontrol = 110; //Bitwise or.
            end  //  <-------- This was missing.
        default: // Default Fall

The 2nd compile error is fixed by changing:

                destres = intsr[20:16];
                //    ^     ^

to:

                destreg = instr[20:16];

Why do I get Syntax Error in Assignment statement l-value?

1 Answers1