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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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How Quartus optimize your circuit?

I am using Altera FPGA to design some circuits. During synthesis with Quartus, I found that if I give different input signals (my input signal is a .hex file that stored a bunch of instructions), the logic elements consumption is different. For…
Shuaiyu Jiang
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How to configure PCI Express hard ip in Stratix IV?

I want to use PCI Express for my upcoming project. So before working for my project I want to do some basic exprements with PCI express. I tried PCI Express reference for stratic IV and it was succesful. As a next step I want to either modify the…
teenu
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DE1-SoC Board FPGA for evolvable hardware

I would like to reproduce the experiment from Dr. Adrian Thompson, who used genetic algorithm to produce a chip (FPGA) which can distinguish between two different sound signals in a extreme efficient way. For more information please visit this…
IMC
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How to detect on which Altera FPGA I am from software running on NIOS2 processor

I think my title says it all. I am running a software on a NIOS2 processor on an Altera FPGA. Is there some way to detect which is the FPGA that the software is running on? To answer the question in the comment: Why do I care which FPGA I am on? For…
Ofer Saferman
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FDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ###

I'm following the tutorial to install linux on SoCkit by Terasic. This is my first time building a linux, so I am still learning. I was able to complete all the steps shown in the tutorial but when I try to boot it gives me error saying: Did not…
Karthik
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C to NIOS II program

I need to write the following C code in NIOS II assembly code. and know the stack state from the L1 label. struct lelt { int value; struct lelt* next; } struct lelt x = {3,NULL}; lelt* get_tail(lelt *ptr) { lelt* last; L1: last =…
jack bloom
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QuartusII 14.1.0 Debian Linux crash

I can't use Quartus 14.1.0 with Linux Debian (wheezy and Jessie) on my 64 bits computer. If I launch it on console I've got this message : user@fpgaformation:/opt/altera/14.1/quartus/bin$ ./quartus Inconsistency detected by ld.so: dl-close.c: 743:…
FabienM
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Does Quartus II support line.all?

I implemented some VHDL code to exports FSM state encodings at compile time, which can be read back by Xilinx ChipScope. This functionality is tested with Xilinx ISE 14.7, iSim 14.7 and Mentor Graphic's QuestaSim 10.2c. My design can be synthesized…
Paebbels
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Shifting and adding a std_logic_vector (has 36 but must have 18 elements)

I'm facing some weird errors from quartus when I try this. Here's the code (all the unsigned & other weird functions was my attempt at persuading Quartus to compile it.) library ieee; use ieee.std_logic_1164.all; use…
MightyPork
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what is the solution of Error in TCl script?

I recently downloaded Modelsim 10.1 from altera.com and i am getting this message of "Error in TCL script". I am not able to start a new verilog project. Here is the error Trace back: can't read "Project(SaveCompileReport)": no such element in…
rahuldce
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Cortex-A9 Cache Parity

I'm using a cortex-a9 based design ( Altera Cyclon-V ) with a pl310 l2 cache controller. When I'm enabling the "parity enabled" in the PL310 AUX register, I get failures ( interrupt indicating cache parity issue ) . When I'm keeping Parity…
user3087632
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Unsupported feature error

I am trying to compile this piece of code in VHDL, using Altera 10.2, but I get this error: Unsupported feature error: non-locally-static attribute names are not supported I asked my instructor some help on this error message, but he said that my…
Dimitris Sapikas
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Read first synchronous RAM in Altera Quartus for Cyclone II

is there a simple way to make inferred synchronous RAM with read-first then write logic for Altera Cyclone II? I need this to implement cancel option into my RAM’s driver. I am thinking about some state machine that first reads the memory and…
silmeth
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Why IEEE vhdl standard library is not STL?

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator. It seems that Altera's…
Jichao
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Conversion from numeric_std unsigned to std_logic_vector in vhdl

I have a question related to conversion from numeric_std to std_logic_vector. I am using moving average filter code that I saw online and filtering my ADC values to stable the values. The filter package code is: library ieee; use…
user3008991
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