Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

Stratix
Cyclone
Arria
MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

492 questions

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1 answer

NIOS II - Resetting FPGA from software (reload FPGA configuration, don't just reset processor)

Context I'm writing code that runs in uClinux on a NIOS II processor. The FPGA is a Stratix II. The FPGA design was done by someone else who is no longer at the company and I'm not a firmware designer, just a software programmer. Problem The FPGA…

asked Oct 16 '15 at 13:20

Sonic Atom

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1 answer

How to concatenate strings with integer in report statement?

I'm having trouble getting the following report statement to work: report "ERROR: instruction address '" & CONV_INTEGER(a(7 downto 2)) & "' out of memory range." severity failure; Where a is of type in std_logic_vector(31 downto 0). The error I'm…

vhdl modelsim intel-fpga quartus

asked Apr 16 '15 at 18:20

Nate

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214

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4 answers

Using Quartus from command line

I am trying to use Quartus II 13.0 (Free Web Package) on Linux (Kubuntu 12.04 LTS) from the command line to generate Verilog technology netlists from Verilog RTL. I need this for a project where I compare the synthesis results produced by different…

verilog fpga intel-fpga

asked Jul 03 '13 at 09:45

CliffordVienna

7,995
1
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57

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1 answer

Can't infer register for ... at ... because it does not hold its value outside the clock edge

This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's…

vhdl fpga intel-fpga

asked May 13 '11 at 03:26

Harold Forrest

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2 answers

Shifter output is always 0 when using concatenation and case

I have the following code: module shifter( input[7:0] in, input[1:0] amt, output logic[7:0] out ); always_comb case(amt) 2'h0: out = in; 2'h1: out = {{in[6:0]}, 0}; 2'h2: out = {{in[5:0]}, 0, 0}; 2'h3: out = {{in[4:0]},…

verilog system-verilog modelsim intel-fpga

asked Jun 14 '18 at 06:28

jeanluc

1,608
1
14
28

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1 answer

VHDL integer range inclusive? Difference in FPGA vs. simulation

I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand. I have a 50MHz clock source. I have a signal defined as: SIGNAL ledCounter : integer range 0 to 25000000 := 0; When the ledCounter reaches…

vhdl fpga modelsim intel-fpga

asked Mar 11 '15 at 19:10

RobC

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3 answers

How to generate .rbf files in Altera Quartus?

What are .rbf files and how can i generate them from the Quartus output file .sof on windows ?

fpga intel-fpga quartus

asked Mar 01 '15 at 22:28

Eslam Medhat

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1 answer

Why using two flip-flops instead of one in this Verilog HDL code?

This code is a button debouncer. But I can't understand why there are two flips flops : reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high reg PB_sync_1; always @(posedge clk) PB_sync_1 <=…

verilog fpga hdl intel-fpga

asked Jul 09 '14 at 17:38

user3821562

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4 answers

Nios 2 "Hello World"?

I've managed to run a complicated project on the Nios 2 Altera DE2 board where I created a timer with assembly and C code using the input and output. With the Nios 2 IDE I can download the project to the DE2 FPGA and the clock runs as expected. But…

c fpga intel-fpga nios

asked Jul 31 '13 at 09:13

Niklas Rosencrantz

25,640
75
229
424

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1 answer

System Console over JTAG fails to execute master_write_32 — can't do this while target is running?

I had a simple controller written in Verilog that was configuring Altera's TSE MAC. Up to this point, it was fairly simple. However, what I wanted to do next is to set a lot of Marvel PHY's settings as well as keep monitoring both PHY and MAC for…

embedded fpga jtag intel-fpga system-console

asked Jul 22 '12 at 15:50

user405725

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1 answer

Reinventing the Mouse sanity check

I'm essentially creating a new way to control the cursor on the screen. Right now I have an Altera Stratix iv FPGA, and I'd like it to send information via USB to the computer and control the cursor. Is this doable, and does anyone know of…

usb mouse fpga intel-fpga

asked May 15 '12 at 22:11

ZacAttack

2,005
5
21
34

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1 answer

What kind of file for passive parallel loading of Cyclone 10 FPGA?

A total FPGA noob here so be gentle please. I have a Cyclone 10 CL006 connected to a microcontroller. Want to load it by a "Fast Passive Parallel" method. My FPGA engineer sent two files: .sof and .rpd. The .rpd sounds like suitable for the task. Do…

fpga intel-fpga

asked Jan 01 '20 at 23:43

ddbug

1,392
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11
25

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1 answer

How to assign pins in Quartus II

We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to…

vhdl intel-fpga quartus

asked Apr 11 '11 at 11:46

shieldfoss

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1 answer

problems writing to an avalon slave module

I'm woring on a project for an assingment where I need to be able write data to an avalon slave module to select data from 2 different inputs on a nios system running on a DE0 board. After much toiling, I've been unable to write data from the C app…

vhdl fpga intel-fpga nios

asked Aug 18 '17 at 23:04

Andrew Ellis

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1 answer

Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well. Is there a way to reset the contents back to zero without…

verilog vhdl fpga intel-fpga

asked Oct 19 '10 at 08:39

Thomas

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