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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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VHDL - DE0 - QUARTUS II PLL not showing output in modsim

Hi I am trying to use a phased lock loop for clock generation for a VGA controller. I had no luck and decided to make my own clock which then worked fine. I got the VGA controller working. Going back to PLL's though I still can't get a PLL selected…
hoboBob
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ModelSim does not compile overloaded functions and undefined range types

I'm running ModelSim 10.3d, and I have this code in a package: package core_params_types is type array_1d_logic is array (natural range <>) of std_logic; type array_1d_logic_vector is array (natural range <>) of std_logic_vector (natural range…
Raul
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Complex floating-point sequential logic in Verilog

I'm trying to write a synthesizable 3D rasterizer in Verilog/SystemVerilog. The rasterizer right now is not really a 3D rasterizer: it just receives six 32-bits floats for vertex position (vertA_pos_x, vertA_pos_y, vertB_pos_x, vertB_pos_y,…
Gui Prá
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Altera OpenCL parallel execution in FPGA

I have been looking into Altera OpenCL for a little while, to improve heavy computation programs by moving the computation part to FPGA. I managed to execute the vector addition example provided by Altera and seems to work fine. I've looked at the…
Josh
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How to Get Audio Out via the Wolfson WM8731 CODEC on the Altera DE2-115 educational FPGA board?

My group and I are trying to create a synthesizer out of a DE2-115 board for our undergraduate capstone project. The only thing we can't figure out is how to get the frequencies mapped to the "keys" outputted properly through the audio port on…
Sebastian Witkowski
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Extracting Memory Initialization File (MIF) from a BMP photo

I am working on the DE12-115 microprocessor from Altera using Quartus. In order to display a BMP image onto a monitor using the built-in VGA connections, I must first transform the BMP image into its MIF Format. The MIF format will be nothing but a…
TheLebDev
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How can I achieve something similar to Xilinx' RLOC in Altera FPGAs?

I have so far not found any way to do anything similar to Xilinx' RLOC constraints for Altera FPGAs. Does anyone know a way to do this? For example place two FFs in the same or adjacent LABs
AxelOmega
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Automated test runs with Altera Quartus

I have an FPGA design in QuartusII, and a continuous integration server with some spare capacity. Now I'd like to build a testsuite for my FPGA design, where input signals are generated by dedicated components, and the output signals checked against…
Simon Richter
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Compiling *.vhdl into a library, using Altera Quartus II

I am trying to use 'Floating point and Fixed point package' as a part of my filter design in VHDL. I am using Altera Quartus II as the development environment. I downloaded the file package from the website: http://www.vhdl.org/fphdl/, now available…
ElectroJunkie
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VHDL - Incrementing Register Value on Push Button Event

I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to…
John Roberts
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Trying to blink LED in Verilog

I have a CPLD with a 50Mhz clock. This is my code: module FirstProject(clk, LED); output LED; input clk; reg [32:0] count1; reg LEDstatus; assign LED = LEDstatus; always @ (posedge clk) begin if (count1 < 10000000) begin …
Brian Gorman
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Altera Qsys and top level entity with array of std_logic_vector

I have been trying to declare my type in a separate "mytypes.vhd" file as follows: library ieee; use ieee.std_logic_1164.all; package mytypes is type my_bus_array_type is array (0 to 3) of std_logic_vector(7 downto 0); end package mytypes; and…
kean
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Design of compression using OpenCL FPGA

I am working on a lossy compressor, and I am wondering which way is more suitable for the design, the first one is to transfer data to the global memory until all the data is processed and the second way is to use either pipes or channels to pass…
Hazim Hamad
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In Intel Quartus, can I initialize RAM using a string parameter?

I need to initialize several instances of the same ram module with different data files which I would like to do as follows: module ram #( string HEXFILE = "split1.mem" ) ( input logic clk, input logic [31:0] a, input logic [7:0] …
Plasty Grove
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Shift Right And Shift Left (SLL/SRL)

so, I'm developing an ALU for MIPS architecture and I'm trying to make a shift left and a shift right so that the ALU can shift any amount of bits. the Idea I had is to convert the shift value to an integer and select the piece of the entry that'll…
Adriano
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