Stack Overflow
Stack Overflow

Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

492 questions
2
votes
1 answer

Using usb keyboard on FPGA Boards (VHDL)

I'm currently coursing computer's structure class, Our teacher has claimed that is impossible to use the USB interface to read keyboard inputs, I've searched online and haven't found any information related, there are tons of tutorials using the…
Mauricio Guzmán
  • 43
  • 10
2
votes
1 answer

Trying to find Fmax in VHDL but getting extra cycle of delay

I want to see the speed of my VHDL design. As far as I know, it is indicated by Fmax in the Quartus II software. After compiling my design, it shows an Fmax of 653.59 MHz. I wrote a testbench and did some tests to make sure that the design is…
gilianzz
  • 199
  • 2
  • 14
2
votes
0 answers

Cannot use component in function

Assignment: Write a package declaration that declares: 1) (25 Pts) User defined type for BCD (Binary Coded Decimal) for 4 digit decimal numbers (In BCD notation four bits are used to indicate a decimal digit. Hence, the two digit decimal number…
user3720045
  • 33
  • 2
  • 4
2
votes
2 answers

Measure Power Consumption of Designed system on an Altera DE1 Board

I am designing a processor using an Altera DE1 kit. I will be running test bench to stress the processor. I want to know if there is any way to measure only the power consumption of my design and neglecting the other power dissipation caused by the…
Adaptive
  • 21
  • 3
2
votes
1 answer

Maximum frequency of my FPGA design in Quartus (Altera)

I've been told that during compilation maximum frequency of the compiled design is estimated and can be viewed somewhere in logs - my problem is, I cannot find it. Any idea to where it's located in Quartus 13.0? Screenshot would be great, thanks in…
Benji
  • 23
  • 1
  • 5
2
votes
0 answers

Can't find VisualStudio linker LINK.EXE

I'm following the openCl documentation provided by Altera to setup an FPGA board and run an example on it. So far I have installed the SDK and followed the instructions but when I get to the step where I have to compile the kernel, I get the…
Tim McGrand
  • 77
  • 1
  • 1
  • 8
2
votes
2 answers

How to check the throughput and latency in Altera OpenCL

In altera design example, I tried vector add but I can't get the throughput and latency of kernel from the compilation results. I read the programming guide of Altera. It mentioned to use profile.mon. Is it possible to use -march=emulator --profile…
dev_55
  • 21
  • 3
2
votes
0 answers

16-bit floating point on fpga

I try to use Altera's floating point IP to generate half precision instead of single (32-bit) blocks for addition , multiplication etc. However when configuring the IP it seems that half precision fp needs a lot more LUTs and has far more latency in…
user2609910
  • 157
  • 8
2
votes
2 answers

modelsim script on start up

I run ModelSim (Altera 13.1 SE) and I want following: 1. Load file tb.wlf 2. Add all signals to wave I do this: vsim tb.wlf -do "add wave -r /*" or vsim -do "vsim tb.wlf;add wave -r /*". Modelsim reads all script, loads signals from tb.wlf but…
Victor Akhlynin
  • 51
  • 7
2
votes
2 answers

Does not work as before Verilog initial construction in ModelSim Altera Edition 10.4

Since version 10.4, start problem with initial block. Like this: reg [31:0] init_ram[15:0]; initial begin init_ram[0] = 32'h1234_5678; init_ram[1] = 32'h8765_4321; ... end always_ff @(posedge clk) init_ram[addr] <= data; Or module…
Papayaved
  • 103
  • 1
  • 1
  • 11
2
votes
1 answer

Maximum clock frequency on DE1-SOC

What is the maximum clock frequency that can be generated with Altera PLLs in DE1-SOC board?
MTMD
  • 1,162
  • 2
  • 11
  • 23
2
votes
2 answers

OpenCL Matrix Multiplication Altera Example

I am very new to OpenCL and am going through the Altera OpenCL examples. In their matrix multiplication example, they have used the concept of blocks, where dimensions of the input matrices are multiple of block size. Here's the code: void…
user3509540
  • 41
  • 1
  • 7
2
votes
1 answer

RTL Viewer Command line

What is the command to run Alter Quartus RTL Viewer, or ModelSim RTL from the Command line under Windows? I tired the following command, however RTL Viewer window does not appear quartus_rpp t -c t --netlist_type=sgate where t is my project's name…
Haskell00
  • 63
  • 1
  • 10
2
votes
2 answers

wait statement must contain condition clause with UNTIL keyword

The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't…
aviv yaakobi
  • 21
  • 1
  • 1
  • 4
2
votes
1 answer

Using De2-115 board to run a project developed on a different board?

I am trying to run different open source projects/games on my DE2-115 Altera board, however, these projects are usually developed on different boards like: Xilinx Spartan 3, DE0, DE1, ...etc. My question is, what are generally the things I need to…
newbie
  • 23
  • 3
1 2 3
…
32 33