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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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How do I save key-press entries on a PMOD keypad for FPGA

I have a DE-10 lite FPGA with the Digilent PMOD Keypad and I'm trying to increment a counter every time a button on the keypad is pressed. I'm trying to increase a counter so that I may know how many buttons have been pressed while in the current…
nick n
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How to fix Error (10170): Verilog HDL syntax error at near text "("; expecting ";"

I am trying to instantiate a NiosII core in Quartus II and get the following compilation error message: Error (10170): Verilog HDL syntax error at myNiosII_inst.v(1) near text "("; expecting ";" I added myNiosII.qip and myNiosII_inst.v files to my…
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rs232 receiver in VHDL doesn't hold data correctly if at all

I'm trying to design a rs232 receiver in VHDL : I send numbers with a python script that it have to catch and show to some leds. I hope to have understood how RS232 works and went to work to make that design. The design doesn't behave the way I hope…
NRagot
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Random number in C

I'm writing my own method to generate a random number with C as follows: int randomNumber(){ int catch = *pCOUNTER; int temp = catch; temp /= 10; temp *= 10; return (catch - temp); } pCounter is basically a pointer…
Sadiq
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Verilog Increment Decrement counter using Altera Board

Hey so I'm basically brand new to Verilog and not quite sure how the syntax works and things like this. The assignment is as below Use a push button and a switch on the Altera board to increment or decrement a 4 bit counter. The value of the…
Lucas Wetherall
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How to use sin, arcsin functions in vhdl Quatus 2 16.1 Lite?

I am using Quatus 2 Prime 16.1 Lite version. what i am trying to do as follows, I have compiled float_pkg_c,fixed_pkg_c under ieee_proposed library as in shown in below link in comment. and i am using to_float to convert real variable to std logic…
iopertyki
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FPGA MOTOR CONTROL

I'm going to implement a motor control based on FPGA with a NIOS II soft processor, I need the system to meet the requirements of TUV and IEC 61508 certificates. I have read one solution to use a redundancy system, but I couldn't understand how I…
Abdullah Salah
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Build uClinux for FPGA?

I want to build a Linux for my Altera DE2-115 that connects with the serial port. Now I see kernel panic from the serial port when I try and run it: 0.000000] Linux version 4.8.0+ (developer@developer-Latitude-E7450) (gcc version 6.2.0 (Sourcery…
Niklas Rosencrantz
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" top level design entity is undefined" ... what does it mean?

this is the code and saved it as IR.vhd, while the name of the project is saved as "8051" when i try to compile a vhdl program in altera it is showing "Error (12007): Top-level design entity "8051" is undefined " ... what does it mean ? library…
varun
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Verilog code 2 errors i can't find: Would be grateful for an extra pair of eyes to spot a mistake i might've overlooked

I'm writing a verilog code where i'm reading two files and saving those numbers into registers. I'm then multiplying them and adding them. Pretty much a Multiplication Accumulator. However i'm having a hard frustrating time with the code that i…
user3859049
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How to setup the control interface for the Avalon-MM?

In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported. Now I struggle to setup the control interface to access the ADC channels. Mainly…
Norick
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Altera UART IP Core

I am trying to make some tests with an FPGA and while trying to add an UART to my design using the Quartus II v13.0 SP1 and the Megawizard plug-in I realised that there is no UART available there but it is available from Qsys tool. My question is…
osuarez
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vhdl manual clock hour set

I am trying to make an alarm clock for a final project in one of my classes. I am using push buttons on a DE1 Altera board to manually increment hours and mins. The mins work but I can not get the hours to increment manually. All pin assignments are…
ALTHEPAL
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Altera Quartus and modelsim

I am writing something in verilog in quartus, and appeared to me something strange, but pretty simple actually This code increments the address correctly module counter( input wire clock, input wire reset, output reg…
Douglas Cerqueira
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Issues Regarding Quartus Synthesis Running Time

I am running Quartus II 13.0sp1 (64-bit) Web Edition. I used to design my modules in ModelSim simulator. Unfortunately, when I tried to test my program using the Altera Kit via Quartus II 13.0sp1. It takes so long time to run the program. Beside the…
user3300910
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