Cortex-A9 Cache Parity

Question

I'm using a cortex-a9 based design ( Altera Cyclon-V ) with a pl310 l2 cache controller. When I'm enabling the "parity enabled" in the PL310 AUX register, I get failures ( interrupt indicating cache parity issue ) . When I'm keeping Parity disabled (default value) system runs fine, no error\abort of bad data.

Any ideas why this might happen?

Some PL310 have the extra parity cache bits and some don't. It is obviously less SRAM cells to not have parity so I guess that most designs do not populate it. If you enable it and there is no parity cells on chip, you will get an error. You have to look at the cache ID registers. For the comments, it seems the OP has the parity bits in the design. — artless noise, Jan 05 '15 at 20:37

score 0 · Answer 1 · answered Jan 24 '14 at 16:23

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A few things that you should check up on is errata for the device that you are using and any specific recommendations on the operating frequency of the CPU to use certain features.

Early version of PL310 had a few bugs around the parity feature and a quick search also turns up the following document from Altera for the Cyclon-V devices. It recommends certain operating frequencies when using the ECC feature and the issue that you are seeing could be similar.

answered Jan 24 '14 at 16:23

vPraetor

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Thanks . I'm aware of this ECC bug. Altera Cyclone V offers both Parity Check ( on Tag RAM ) and ECC ( on Data RAM ). we are aware of the ECC Errata. The Aborts we are seeing are a result of Parity failures on Tag RAM. I've modified some timing register (read\write cycles) and it seems more stable now, although I'm still not sure what caused the issue to begin with – user3087632 Jan 30 '14 at 19:51
Are you referring to the timing registers for PL310? If so, you need to ensure you don't go lower than what the chip was validated for. I don't know if the most optimum setting for this particular device is documented somewhere. It typically comes out in the initial design phase and may not be available in the usual docs. Do keep in mind that when using a setting that was never validated all bets are off. – vPraetor Jan 31 '14 at 01:11

score 0 · Answer 2 · answered Jan 27 '14 at 13:56

Parity is one way of checking that the memory locations have not been corrupted. With parity disabled, then you will not get errors or aborts, as nothing is checking the data.

With parity enabled, you have two potential causes of the aborts;

The memory system you have connected the cache controller to does not perform the parity checking the same way as the controller expects (or possibly not at all!)
You have an actual problem with the cache memory.

If you have the first problem, you need to decide if it is important and if so, configure, or implement (or buy!) a cache controller that works the way your system needs it to.

If you have the second problem, well, at least you know about it now, which you wouldn't have with parity disabled. It still needs fixing though!

Cortex-A9 Cache Parity

2 Answers2