2

is there a simple way to make inferred synchronous RAM with read-first then write logic for Altera Cyclone II?

I need this to implement cancel option into my RAM’s driver.

I am thinking about some state machine that first reads the memory and remembers it in DFF and after that writes to it, but honestly, I have no idea how to even start writing it. And maybe there’s simpler solution?

silmeth
  • 680
  • 1
  • 8
  • 22
  • What tools? The synthesiser manual ought to have a section with templates that you can copy from... – Martin Thompson Jan 06 '14 at 21:44
  • Altera Quartus. Well, as I commented under Michael Roland’s answer – it seems M4K memory blocks allows creation of 1-port RAM with read-first behavior but only write-first for 2-port RAM. At the beginning I was trying 2-port and then assumed it also won’t work with 1-port. Hence my problem… – silmeth Jan 06 '14 at 22:52

1 Answers1

3

Something like this should result into the desired behavior (read old value and write new value):

process (clk)
begin
  if (clk'event and clk = '1') then
      if (write_enable = '1') then
          ram_block(write_address) <= new_data;
      end if;
      old_data <= ram_block(read_address);
  end if;
end process;
Michael Roland
  • 39,663
  • 10
  • 99
  • 206
  • OK. It seems you are right. I was trying before making two-port RAM with read-first behaviour and it is impossible using Cyclone II to infer this. I assumed it is impossible also with 1-port RAM. I was wrong, and it is indeed doable. So one needs to choose: either only one port and read-first or two ports but only write-first behaviour. – silmeth Jan 06 '14 at 22:50
  • With dual-ported RAM there is the problem that there is no defined relationship between the two port's clocks. So there is no way to correlate read and write. Moreover, even if both clocks are the same signal, VHDL semantics would not let you design this in a two-process approach. – Michael Roland Jan 07 '14 at 19:32
  • Well, it *is* used in opencores w11 project (http://opencores.org/project,w11) which I was trying to run on Altera Cyclone II. Eventually I used write-first 2-port RAM, which would sometimes generate some errors (doesn’t let you cancel write) but otherwise mostly works. – silmeth Jan 22 '14 at 20:07
  • I assume you are refering to [this](http://opencores.org/websvn,filedetails?repname=w11&path=%2Fw11%2Ftrunk%2Frtl%2Fvlib%2Fmemlib%2Fram_2swsr_rfirst_gen.vhd), right? If yes and you use it with one port to read only and one port to write only (both ports fed with the same clock signal), I suggest you try simulating with read and write port switched and compare simulation results (or you may also simply move the process for port B above the process of port A). That's the case I was refering to and I assume the result is *not* what you would desire. – Michael Roland Jan 22 '14 at 22:18