Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

Stratix
Cyclone
Arria
MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

492 questions

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Is there a way to make Quartus II to support PAL devices?

I use in school the Galaxy to write and compile VHDL programs, but it only runs on Windows XP and I don't have it. I installed Quartus II in my computer (I use Ubuntu), but apparently there is no support for PAL devices (specifically GAL22V10D). It…

asked Jan 28 '14 at 01:26

Adrian

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1 answer

How does a TABLE work in AHDL?

I have an implementation of a Control Unit (UC) in AHDL, and I'm supposed to simulate it and see if it works as defined in the correspondent ASM diagram. I used MAX+plus II to simulate it, and it doesn't work as I expected, but I can't really say…

hardware simulation intel-fpga

asked Oct 28 '09 at 13:57

dsetton

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0 answers

Intel oneAPI - Supported Development Devices

I've read this morning something that now seems to be a sales-pitch, about Intel's oneAPI that let's you design hardware for "any development platform" (something along those lines). So I assumed that I'd be able to use my old development…

fpga intel-fpga intel-oneapi

asked Aug 11 '23 at 19:58

Laserbeak43

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1 answer

Timing diagram of convst. signal of ADC (ads8556)

I want to work on ADC (ads8556). In Figure 3 In the Parallel Read Access Timing Diagram, when the conversion time (tconv) finishes, and during the acquisition time (tACQ), there are multiple transitions in the level state of convst signal changes…

adc intel-fpga texas-instruments

asked Jun 23 '23 at 09:09

hasan altaey

-2

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1 answer

In Verilog, how to connect an input of a block to ground (essentially the input = 0 value)

So I am making an ALU that has an 8to1 mux that selects between different operations. However only 6 operations are required, so the other two inputs of the mux don't even need to be used. So is there a way to essentially connect them to gnd?…

verilog fpga intel-fpga

asked Mar 13 '21 at 19:56

RhinoECE

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1 answer

How to implement several independent devices on one FPGA?

I need implement 2 or more independent device on FPGA (Altera Cyclone III). For example: two counters by one and by two. How I do this make? And how to use this devices parallel? Thanks everybody!

vhdl fpga intel-fpga

asked Jul 03 '19 at 17:22

Pavlishin Nikita

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2 answers

How to calculate sin inverse (arcsin) in VHDL?

I am using Altera De0 nano Soc FPGA, and Quartus 16.1 lite edition. After doing a search on internet, I found that to get sin, cos and atan Altera's CORDIC IP core can be used directly. And also found lookup table (LUT) can be used for sin or cos…

vhdl lookup-tables intel-fpga inverse cordic

asked Jun 29 '17 at 04:43

komto909

-2

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2 answers

How to convert rpm to rad/s in C?

How to convert rpm to rad/s in C? I am using Altera Monitor program to compute rad/s from rpm. but when i use 2*pi/60 it says "pi" is not declared.I have included math.h still it same issue. also i have another problem when including vhdl floating…

c vhdl intel-fpga

asked Jun 25 '17 at 07:15

gobsa89

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1 answer

5 seconds Timer in VHDL

I am using 50MHz clock in fpga and trying make 5 seconds timer. below cnt_t reach to 5 x 50MHz (x"0EE6B280" --> 250,000,000) then make time_tick_32 to 1 and make cnt_t <= x"00000000";. The code below did not work never time_tick_32 gets 1. signal…

timer vhdl counter intel-fpga

asked May 01 '17 at 20:17

iopertyki

-2

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1 answer

What does this line mean in verilog?

From http://www.johnloomis.org/digitallab/lcdlab/lcdlab3/lcdlab3.qdoc.html How can I change DATA_BUS so that it is not using inout. // BIDIRECTIONAL TRI STATE LCD DATA BUS assign DATA_BUS = (LCD_RW_INT? 8'bZZZZZZZZ: DATA_BUS_VALUE)

verilog fpga lcd intel-fpga

asked Mar 05 '17 at 23:41

Edward Elric

-3

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1 answer

How to Interface 16 * 2 LCD(HD44780) using Verilog to FPGA/CPLD?

I want to interface a 16 character * 2 line LCD (HD44780) to my FPGA board using Verilog HDL. The program I wrote does not work at all and I don't know why, even though I made a state machine and inserted delays. Note that I used 8 bit mode. Here is…

verilog fpga xilinx system-verilog intel-fpga

asked Feb 06 '14 at 17:48

Shrikant Vaishnav

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